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T5760 Datasheet(PDF) 20 Page - ATMEL Corporation

Part # T5760
Description  UHF ASK/FSK Receiver
PDF  32 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

T5760 Datasheet(HTML) 20 Page - ATMEL Corporation

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T5760 T5761
/
Rev. A2, 19-Oct-00
Preliminary Information
20 (32)
Table 10 Effect of the configuration word Lim_min
Lim_min *) (Lim_min < 10 is not applicable)
Lower Limit Value for Bit Check
Lim_min5
Lim_min4
Lim_min3
Lim_min2
Lim_min1
Lim_min0
(TLim_min = Lim_min y XLim y TClk)
0
0
1
0
1
0
10
0
0
1
0
1
1
11
0
0
1
1
0
0
12
.
.
.
.
.
.
.
.
.
.
.
.
0
1
0
1
0
1
21 (Default)
(TLim_min = 347 µs for fRF = 868.3 MHz and BR_Range0
TLim_min = 329 µs for fRF = 915 MHz and BR_Range0)
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
0
1
61
1
1
1
1
1
0
62
1
1
1
1
1
1
63
*) Lim_min is also be used to determine the margins of the data clock control logic (see chapter ’Data Clock’)
Table 11 Effect of the configuration word Lim_max
Lim_max *) (Lim_max < 12 is not applicable)
Upper Limit Value for Bit Check
Lim_max5
Lim_max4
Lim_max3
Lim_max2
Lim_max1
Lim_max0
(TLim_max = (Lim_max – 1) y XLim y TClk)
0
0
1
1
0
0
12
0
0
1
1
0
1
13
0
0
1
1
1
0
14
.
.
.
.
.
.
.
.
.
.
.
.
1
0
1
0
0
1
41 (Default)
(TLim_max = 677 µs for fRF = 868.3 MHz and BR_Range0,
TLim_max = 642 µs for fRF = 915 MHz and BR_Range0)
.
.
.
.
.
.
.
.
.
.
.
.
1
1
1
1
0
1
61
1
1
1
1
1
0
62
1
1
1
1
1
1
63
*) Lim_max is also be used to determine the margins of the data clock control logic (see chapter ’Data Clock’)
Conservation of the Register Information
The T5760/T5761 implies an integrated power-on reset
and brown-out detection circuitry to provide a mecha-
nism to preserve the RAM register information.
According to figure 30, a power–on reset (POR) is gener-
ated if the supply voltage VS drops below the threshold
voltage VThReset. The default parameters are pro-
grammed
into the configuration registers in that
condition. Once VS exceeds VThReset the POR is canceled
after the minimum reset period tRst. A POR is also gener-
ated when the supply voltage of the receiver is turned on.
To indicate that condition, the receiver displays a reset
marker (RM) at Pin DATA after a reset. The RM is repre-
sented by the fixed frequency fRM at a 50% duty-cycle.
RM can be canceled via a Low pulse t1 at Pin DATA. The
RM implies the following characteristics:
D fRM is lower than the lowest feasible frequency of a
data signal. By this means, RM cannot be misinter-
preted by the connected
µC.
D If the receiver is set back to polling mode via Pin
DATA, RM cannot be canceled by accident if t1 is ap-
plied according to the proposal in the section
’Programming the Configuration Registers’.
By means of that mechanism the receiver cannot lose its
register information without communicating that condi-
tion via the reset marker RM.



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