T5761

T5760 /

Preliminary Information

Rev. A2, 19-Oct-00

21 (32)

V

S

POR

Data_out (DATA)

1 / f

RM

t

Rst

V

ThReset

X

Figure 30. Generation of the power-on reset

Programming the Configuration Register

Out1 (

Data_out (DATA)

Serial bi–directional

data line

X

Bit 1

(”0”)

Bit 2

(”1”)

Bit 14

(”0”)

Bit 15

(”0”)

X

t1

t2

t3

t4

t5

t6

t8

t7

Programming frame

(Start bit)

(Register–

select)

(Poll8)

(Stop bit)

Receiving

mode

Start–up

mode

t9

IC_ACTIVE

TSleep TStart–up

Sleep

mode

Figure 31. Timing of the register programming

Data_In

Data_out

Input –

Interface

DATA

0 ... 20 V

0 V / 5 V

V

R

pup

C

L

VS = 4.5 V to 5.5 V

I/O

Serial bi–directional data line

T5760/

T5761

µC

Out1

µC

Figure 32. Data interface

The configuration registers are programmed serially via the bi-directional data line according to figure 31 and figure

32.