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F530SL Datasheet(PDF) 1 Page - Fox Electronics

Part # F530SL
Description  3.3V HCSL Oscillator
PDF  3 Pages
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Manufacturer  FOX [Fox Electronics]
Direct Link  http://www.foxonline.com
Logo FOX - Fox Electronics

F530SL Datasheet(HTML) 1 Page - Fox Electronics

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3.3V HCSL Oscillator
MODEL: F530SL Series RoHS Compliant / Pb Free / REACh Compliant Rev 11/26/2013
Preliminary Specifications
FOXElectronics 5570 Enterprise Parkway Fort Myers, Florida 33905 USA +1.239.693.0099 FAX +1.239.693.1554 www.foxonline.comEMEA Tel: +44 .1283.568153 | Canada
+1.888.438.2369 | Japan Tel: +81.3.3374.2079 | Singapore Tel: +65.68447989© 2013 FOX ELECTRONICS | An Integrated Device Technology, Inc. company | ISO9001:2008 Certified
+
FEATURES:
HCSL Differential Output
Low Phase Jitter (under 1pS RMS 12kHz~20MHz)
PART NUMBER SELECTION
Part Number
Model
Number
Frequency
Stability
1
Operating
Temperature
(TOPR) (°C)
Frequency Range
(MHz)
474C-Frequency-xxx
F530SL
±100 PPM
0 ~ +70
15.000 ~ 160.000
475C-Frequency-xxx
F530SLR
±100 PPM
-40 ~ +85
15.000 ~ 160.000
476C-Frequency-xxx
F535SL
±50 PPM
0 ~ +70
15.000 ~ 160.000
550C-Frequency-xxx
F535SLR
±50 PPM
-40 ~ +85
15.000 ~ 160.000
492C-Frequency-xxx
F536SL
±25 PPM
0 ~ +70
15.000 ~ 160.000
636C-Frequency-xxx
F536SLR
±25 PPM
-40 ~ +85
15.000 ~ 160.000
SPECIFICATIONS
PARAMETERS
MAX (unless otherwise noted)
Storage Temperature Range (TSTG)
-55 ~ +125°C
Supply Voltage
(VDD)
3.3V±5%
Input Current
(IDD)
40mA
Output Symmetry (Cross Point)
45% ~ 55%
Rise/Fall Time (0.175 ~ 0.525V)
15.000 ~ 99.999999 MHz
100.000 ~ 160.000 MHz
1.0nS
0.7nS
Output Voltage
(VOL)
(VOH)
-0.15 ~ 0.15V
0.66 ~ 0.85V
Output Swing
(VOPP)
0.65V Min
Output Load
50 Ohms to GND
Standby Current
10uA
Start-up Time
(TS)
10mS
Output Disable Time 2
200nS
Output Enable Time 2
10mS
Aging (per year @ 25C)
±3 PPM
Phase Jitter (12kHz~20MHz)
1pS RMS
Maximum Soldering Temp / Time
260°C / 10 Seconds
Moisture Sensitivity Level (MSL)
1
Termination Finish
Au
1 Inclusive of 25
C tolerance, and operating temperature range.
2 An internal pull-up resistor from pin 1 to pin 6 allows active output if pin 1 is left open.
Notes:
*A 0.01μF capacitor should be placed between VDD (Pin 6) and GND (Pin3) to minimize
power supply line noise.
*Dimensional drawing is for reference to critical specifications defined by size measurements.
Certain non-critical visual attributes, such as side castellations, reference pin shape, etc. may vary
ENABLE / DISABLE FUNCTION
Pin1
Out 1 (pin 4), Out 2 (pin 5)
OPEN 2
Active
‘1’ Level VIH  70%VDD
Active
‘0’ Level VIL  30%VDD
High Z


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