DAC8574IPW datasheet(27/45 Pages) TI

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Power-On Reset

Power-Down Modes

Resistor

String DAC

Powerdown

Circuitry

VOUT

Amplifier

Resistor

Network

DAC8574

SLAS377B – JANUARY 2003 – REVISED DECEMBER 2004

The DAC8574 contains a power-on-reset circuit that controls the output voltage during power up. On power up,

the DAC register is filled with zeros and the output voltage is 0 V; it remains there until a valid write sequence is

made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC

while it is in the process of powering up. No device pin should be brought high before supply is applied.

The DAC8574 contains four separate power-down modes of operation. The modes are programmable via two

most significant bits of the MSB byte, while (CTRL[0] = PD0 = 1). Table 8 shows how the state of these bits

correspond to the mode of operation of the device.

Table 8. Power-Down Modes of Operation for the DAC8574

CTRL[0]

MSB[7]

MSB[6]

OPERATING MODE

High Impedance Output

1 k

Ω to GND

100 k

Ω to GND

High Impedance

When (CTRL[0] = PD0 = 0), the device works normally with its normal power consumption of 250 µA at 5 V per

channel. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not

only does the supply current fall but also the output stage is also internally switched from the output of the

amplifier to a resistor network of known values. This has the advantage that the output impedance of the device

is known while in power-down mode. There are three different options: The output is connected internally to GND

through a 1-k

Ω resistor, a 100 kΩ resistor or left open-circuit (high impedance). The output stage is illustrated in

Figure 55.

Figure 55. Output Stage During Power Down

All linear circuitry is shut down when the power-down mode is activated. However, the contents of the DAC

µs for VDD = 3 V. (See the Typical Curves section for additional information.)

The DAC8574 offers a flexible power-down interface based on channel register operation. A channel consists of

a single 16-bit DAC with power-down circuitry, a temporary storage register (TR) and a DAC register (DR). TR

and DR are both 18 bits wide. Two MSBs represent the power-down condition and the 16 LSBs represent data

for TR and DR. By using bits 17 and 18 of TR and DR, a power-down condition can be temporarily stored and

used just like data. Internal circuits ensure that MSB[7] and MSB[6] get transferred to TR[17] and TR[16] (DR[17]

and DR[16]) when the power-down flag (CTRL[0] = PD0) is set. Therefore, DAC8574 treats power-down

conditions like data and all the operational modes are still valid for power down. It is possible to broadcast a

power-down condition to all the DAC8574s in the system, or it is possible to simultaneously power down a

channel while updating data on other channels.

DAC8574IPW Datasheet(PDF) 27 Page - Texas Instruments

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