OPA192ID datasheet(2/35 Pages) TI1

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OPA192

OPA2192

OPA4192

SBOS620A – DECEMBER 2013 – REVISED JANUARY 2014

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE AND ORDERING INFORMATION(1)

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)

Over operating free-air temperature range, unless otherwise noted.

VALUE

UNIT

Supply voltage

±20 (+40, single supply)

Common-mode

(V–) – 0.5 to (V+) + 0.5

Voltage

Signal input

Differential

(V+) - (V-) + 0.2

terminals

Current

±10

Output short circuit(2)

Continuous

Operating temperature

–55 to +150

°C

Storage temperature

–65 to +150

°C

Junction temperature

+150

°C

Electrostatic

Human body model (HBM)

discharge (ESD)

Charged device model (CDM)

ratings

(1)

Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

(2)

Short-circuit to ground, one amplifier per package.

ELECTRICAL CHARACTERISTICS: VS= ±4 V to ±18 V (VS= +8 V to +36 V)

At TA = +25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2, unless otherwise noted.

OPA192

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OFFSET VOLTAGE

±5

±25

µV

VOS

Input offset voltage

TA = –40°C to +125°C

±75

µV

dVOS/dT

Input offset voltage drift

TA = –40°C to +125°C

(V–) – 0.1 V < VCM < (V+) – 3 V

±0.2

±0.5

µV/°C

Power-supply rejection

PSRR

TA = –40°C to +125°C

±0.3

±1.0

µV/V

ratio

INPUT BIAS CURRENT

±5

±20

Input bias current

TA = –40°C to +125°C

±5

±2

±20

IOS

Input offset current

TA = –40°C to +125°C

±2

NOISE

(V–) – 0.1 V < VCM < (V+) – 3V

f = 0.1 Hz to 10 Hz

1.30

µVPP

Input voltage noise

(V+) – 1.5 V < VCM < (V+) + 0.1

f = 0.1 Hz to 10 Hz

µVPP

f = 100 Hz

10.5

nV/

√Hz

(V–) – 0.1 V < VCM < (V+) – 3 V

f = 1 kHz

5.5

nV/

√Hz

Input voltage noise

density

f = 100 Hz

nV/

√Hz

(V+) – 1.5 V < VCM < (V+) + 0.1

f = 1 kHz

12.5

nV/

√Hz

Input current noise

f = 1kHz

1.5

fA/

√Hz

density

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