5-293

FAST AND LS TTL DATA

SN54/74LS165

Symbol

Parameter

Limits

Unit

Test Conditions

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

tW

CP Clock Pulse Width

25

ns

VCC = 5.0 V

tW

PL Pulse Width

15

ns

VCC = 5.0 V

ts

Parallel Data Setup Time

10

ns

VCC = 5.0 V

ts

Serial Data Setup Time

20

ns

VCC = 5.0 V

ts

CP1 to CP2 Setup Time1

30

ns

CC = 5.0 V

th

Hold Time

0

ns

trec

Recovery Time, PL to CP

45

ns

1 The role of CP1, and CP2 in an application may be interchanged.

DEFINITION OF TERMS:

SETUP TIME (ts) — is defined as the minimum time required

for the correct logic level to be present at the logic input prior

to the clock transition from LOW-to-HIGH in order to be recog-

nized and transferred to the outputs.

HOLD TIME (th) — is defined as the minimum time following

the clock transition from LOW-to-HIGH that the logic level

must be maintained at the input in order to ensure continued

recognition. A negative hold time indicates that the correct

logic level may be released prior to the clock transition from

LOW-to-HIGH and still be recognized.

RECOVERY TIME (trec) — is defined as the minimum time

required between the end of the PL pulse and the clock

transition from LOW-to-HIGH in order to recognize and

transfer loaded Data to the Q outputs.

AC WAVEFORMS

tW

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

1.3 V

CP1

CP2

Q7 OR Q7

Pn

PL OR CP

tPHL

tPLH

PL

CP

trec

Q7 OR Q7

PL

tPHL

tPLH

tW

tW

1/fmax

ts

ts(H)

th(H) ts(L)

th(L)

Figure 1

Figure 3

Figure 2

Figure 4

1.3 V