5-290

FAST AND LS TTL DATA

8-BIT PARALLEL-TO-SERIAL

SHIFT REGISTER

The SN54 / 74LS165 is an 8-bit parallel load or serial-in register with

complementary outputs available from the last stage. Parallel inputing occurs

asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH,

serial shifting occurs on the rising edge of the clock; new data enters via the

Serial Data (DS) input. The 2-input OR clock can be used to combine two

independent clock sources, or one input can act as an active LOW clock

enable.

CONNECTION DIAGRAM DIP (TOP VIEW)

NOTE:

The Flatpak version

has the same pinouts

(Connection Diagram) as

the Dual In-Line Package.

14

13

12

11

10

9

1

2

3

4

5

6

7

16

15

8

VCC

PL

CP2 P3

P2

P1

DS

P0

Q7

CP1 P4

P5

P6

P7

Q7 GND

PIN NAMES

LOADING (Note a)

HIGH

LOW

CP1, CP2

DS

PL

P0 – P7

Q7

Q7

Clock (LOW-to-HIGH Going Edge) Inputs

Serial Data Input

Asynchronous Parallel Load (Active LOW)

Input

Parallel Data Inputs

Serial Output from Last State (Note b)

Complementary Output (Note b)

0.5 U.L.

0.5 U.L.

1.5 U.L.

0.5 U.L.

10 U.L.

10 U.L.

0.25 U.L.

0.25 U.L.

0.75 U.L.

0.25 U.L.

5 (2.5) U.L.

5 (2.5) U.L.

NOTES:

a) 1 TTL Unit Load (U.L.) = 40

µA HIGH/1.6 mA LOW.

b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

Temperature Ranges.

TRUTH TABLE

PL

CP

CONTENTS

RESPONSE

PL

1

2

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

RESPONSE

L

X

X

P0

P1

P2

P3

P4

P5

P6

P7

Parallel Entry

H

L

DS

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Right Shift

H

H

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

No Change

H

L

DS

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Right Shift

H

H

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

No Change

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

SN54/74LS165

8-BIT PARALLEL-TO-SERIAL

SHIFT REGISTER

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

16

1

16

1

ORDERING INFORMATION

SN54LSXXXJ

Ceramic

SN74LSXXXN

Plastic

SN74LSXXXD

SOIC

16

1

D SUFFIX

SOIC

CASE 751B-03

LOGIC SYMBOL

VCC = PIN 16

GND = PIN 8

1 11 12 13 14 3 4 5 6

9

7

10

2

15

DS

CP

Q7

Q7

PL P0P1 P2 P3P4 P5P6 P7