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PCM3003 Datasheet(PDF) 20 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation. Click here to check the latest version.
Part # PCM3003
Description  16-/20-Bit Single-Ended Analog Input/Output STEREO AUDIO CODECs
PDF  23 Pages
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Manufacturer  BURR-BROWN [Burr-Brown (TI)]
Direct Link  http://www.burr-brown.com
Logo BURR-BROWN - Burr-Brown (TI)

PCM3003 Datasheet(HTML) 20 Page - Burr-Brown (TI)

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®
PCM3002/3003
20
LOP:
Bit 5
ADC to DAC Loop-Back Control
When this bit is set to “1”, the ADC’s audio data
is sent directly to the DAC. The data format will
default to I2S. In Format 3 (I2S Frame), Loop-
back is not supported.
LOP
0
Loop-back Disable (default)
1
Loop-back Enable
FMT (1,0) Bit 3:2
Audio Data Format Select
These bits determine the input and output audio
data formats.
FMT1
FMT0
DAC
ADC
Data Format
Data Format
NAME
0
0
16-bit, MSB-first,
16-bit, MSB-first,
Format 0 (default)
Right-justified
Left-justified
0
1
20-bit, MSB-first,
20-bit, MSB-first,
Format 1
Right-justified
Left-justified
1
0
20-bit, MSB-first,
20-bit, MSB-first,
Format 2
Left-justified
Left-justified
1
1
20-bit, MSB-first,
20-bit, MSB-first,
Format 3
I2SI2S
LRP:
Bit 1
Polarity of LRCIN Applies only to
Formats 0 through 2.
LRP
0
Left-channel is “H”, Right-channel is “L”. (default)
1
Left-channel is “L”, Right-channel is “H”.
FIGURE 12. Typical Connection Diagram for PCM3002/3003.
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
+
4.7
µF(2)
4.7
µF(2)
+
+
+
+
1
µF
1
µF
Control
Interface
Audio
Interface
+3V Analog V
CC
Rch In
Lch In
SYSCLK
L/R CLK
BIT CLK
DATA OUT
DATA IN
0.1
µF
and
10
µF(1)
0.1
µF and 10µF(1)
0.1
µF
and 10
µF(1)
4.7
µF(4)
+
4.7
µF(4)
Rch Out(5)
Lch Out(5)
MC(6)/DEM0(7)
MD(6)/DEM1(7)
RST(6)/PDAD(7)
ML(6)/PDDA(7)
ZFLG(6)/20BIT(7)
+
+
4.7
µF(4)
+
10k
Ω
PCM3002/3003
V
CC1
V
CC1
V
INR
V
REFL
V
REFR
V
INL
RST/PDAD
ML/PDDA
SYSCLK
LRCIN
BCKIN
DOUT
V
CC2
AGND1
AGND2
V
COM
V
OUTR
V
OUTL
MC/DEM0
MD/DEM1
ZFLG/20BIT
DIN
V
DD
DGND
NOTES: (1) 0.1
µF ceramic and 10µF tantalum, typical, depending on power supply quality and
pattern layout. (2) 4.7
µF typical, gives settling time with 30ms (4.7µF x 6.4kΩ) time constant in
Power ON and Power-Down OFF period. (3) 1
µF typical, gives 5.3Hz cut-off frequency of input
HPF in normal operation and gives settling time with 30ms (1
µF x 30kΩ) time constant in Power
ON and Power -Down OFF period. (4) 4.7
µF typical, gives 3.4Hz cut-off frequency of output HPF
in normal operation and gives settling time with 47ms (4.7
µF x 10kΩ) time constant in Power ON
and Power-Down OFF period. (5) Post low pass filter with R
IN >10kΩ, depending on requirement
of system performance. (6) MC, MD, ML, ZFLG, RST and 10k
Ω pull-up resistor are for the
PCM3002. (7) DEM0, DEM1, 20BIT, PDAD, PDDA are for the PCM3003.



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