PCM3003 datasheet(22/23 Pages) BURR-BROWN

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PCM3002/3003

EXTERNAL MUTE CONTROL

For Power-Down ON/OFF control without click noise which

is generated by DAC output DC level change, an external

mute control is recommended. The control sequence, which

is external mute ON, CODEC Power-Down ON, SYSCLK

stop and resume if necessary, CODEC Power-down OFF,

and external mute OFF is recommended.

THEORY OF OPERATION

ADC SECTION

The PCM3002/3003 ADC consists of two reference circuits,

a stereo single-to-differential converter, a fully differential

5th-order delta-sigma modulator, a decimation filter (includ-

ing digital high pass), and a serial interface circuit. The

Block Diagram in this data sheet illustrates the architecture

of the ADC section, Figure 1 shows the single-to-differential

converter, and Figure 13 illustrates the architecture of the

5th-order delta-sigma modulator and transfer functions.

An internal reference circuit with three external capacitors

provides all reference voltages which are required by the

ADC, which defines the full scale range for the converter.

The internal single-to-differential voltage converter saves

the space and extra parts needed for external circuitry

required by many delta-sigma converters. The internal full-

differential signal processing architecture provides a wide

dynamic range and excellent power supply rejection perfor-

mance. The input signal is sampled at 64X oversampling

rate, eliminating the need for a sample-and-hold circuit, and

simplifying anti-alias filtering requirements. The 5th-order

delta-sigma noise shaper consists of five integrators which

use a switched-capacitor topology, a comparator and a

feedback loop consisting of a one-bit DAC. The delta-sigma

modulator shapes the quantization noise, shifting it out of

the audio band in the frequency domain. The high order of

the modulator enables it to randomize the modulator out-

puts, reducing idle tone levels.

The 64fS one-bit data stream from the modulator is con-

verted to 1fS 18-bit data words by the decimation filter,

which also acts as a low pass filter to remove the shaped

quantization noise. The DC components are removed by a

high pass filter function contained within the decimation

filter.

THEORY OF OPERATION

DAC SECTION

The delta-sigma DAC section of PCM3002/3003 is based on

a 5-level amplitude quantizer and a 3rd-order noise shaper.

This section converts the oversampled input data to 5-level

delta-sigma format. A block diagram of the 5-level delta-

sigma modulator is shown in Figure 14. This 5-level delta-

sigma modulator has the advantage of improved stability

and reduced clock jitter sensitivity over the typical one-bit

(2 level) delta-sigma modulator. The combined oversampling

rate of the delta-sigma modulator and the internal 8X inter-

polation filter is 64fS for a 256fS system clock. The theoreti-

cal quantization noise performance of the 5-level delta-

sigma modulator is shown in Figure 15.

–

5th SW-CAP

Integrator

4th SW-CAP

Integrator

3rd SW-CAP

Integrator

2nd SW-CAP

Integrator

1st SW-CAP

Integrator

–

1-Bit

DAC

H(z)

Qn(z)

Analog In

X(z)

Digital Out

Y(z)

Y(z) = STF(z) • X(z) + NTF(z) • Qn(z)

Signal Transfer Function

Noise Transfer Function

STF(z) = H(z) / [1 + H(z)]

NTF(z) = 1/ [1 + H(z)]

Comparator

FIGURE 13. Simplified 5th-Order Delta-Sigma Modulator.

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