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SBB503R3SCKA Datasheet(PDF) 3 Page - International Rectifier |
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SBB503R3SCKA Datasheet(HTML) 3 Page - International Rectifier |
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3 / 11 page ![]() www.irf.com 3 SBB SERIES Single Output Enable: An Enable pin is provided to remotely turn the POL on or off. It can also be used for output sequenceing for multiple SBB POL regulators. The nominal threshold relative to the input return (pin 2) is 2.5V. If 3.9 volts or greater are applied to the Inhibit pin (pin 3) then the POL will operate normally. The pin may be left open for normal operation. A voltage of 0.4V or less will cause the SBB POL to shut down. Synchronization: An external synchronization port is provided to allow the multiple SBB POLs to be synchronized to an external frequency source to minimize the noise interference coming from the switching operation of the POLs. The synchronization frequency ranges from 360 KHz to 440 KHz and the synchronization signal port can be driven from 5V logic. The SBB Series POLs use a proven conservative design methodology with careful incorporation of known radiation performance devices and established reliability components. All components are fully derated to MIL-STD-1547. Standard design analyses include stress, thermal, failure modes and effects (FMEA), reliability & worst case and are available upon request. POK:The SBB POL also provides a power ok (POK) output status signal at Pin 11. A logic high signal is present when the POL’s output voltage is greater than 95% of the nominal output voltage. A logic low signal at Pin 11 indicates the POL’s output voltage drops below the output voltage threshold of 95% Remote Sense: Output pins 4 and 5 must be connected to +Sense pin 6 for proper operation. The +Sense pin may be connected remotely to the output line at the load to compensate for a voltage drop in the output line for precise optimum output regulation. The maximum voltage compensation in combination with the output voltage adjustment (if required) is limited to 10% of the nominal output voltage.To enhance the load regulation performance Input Return (Pin 2) may be connected externally to Output Return (Pin 3). |
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