 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
CAT513 Datasheet(PDF) 3 Page - Catalyst Semiconductor |
|
|
|||||||||||||||||||||||||||||
CAT513 Datasheet(HTML) 3 Page - Catalyst Semiconductor |
|
|
3 / 10 page  CAT513 3 Advance Information Doc. No. ___________ 3/01 M-1 DC ELECTRICAL CHARACTERISTICS (Cont.): VDD = +2.7V to +5.5V , VREFH = +VDD, VREFL = 0V, unless otherwise specified Symbol Parameter Conditions Min Typ Max Units FSO Full-Scale Output Voltage VR = VREFH–VREFL 0.99 VR 0.995 VR — V ZSO Zero-Scale Output Voltage VR = VREFH–VREFL — 0.005 VR 0.01 VR V IL DAC Output Load Current —— 1 µA ROUT DAC Output Impedance VDD = +5V —— 100k Ω VDD = +3V —— 150k Ω PSSR Power Supply Rejection ILOAD = 250 nA —— 1 LSB / V TCO VOUT Temperature Coefficient VREFH = +5V, VREFL = 0V —— 200 µV/ °C VDD = +5V, ILOAD = 250nA TCREF Temperature Coefficient of VREFH to VREFL — 700 — ppm / °C VREF Resistance IDD1 Supply Current (Read) Normal Operating — 40 50 µA IDD2 Supply Current (Write) VDD=5V — 1200 2000 µA VDD=3V — 600 1200 µA VDD Operating Voltage Range 2.7 — 5.5 V AC ELECTRICAL CHARACTERISTICS: VDD = +2.7V to +5.5V, VREFH = +VDD, VREFL = 0V, unless otherwise specified Temperature Analog Output Power Supply Symbol Parameter Conditions Min Typ Max Units Digital tCSMIN Minimum CS Low Time 150 —— ns tCSS CS Setup Time 100 —— ns tCSH CS Hold Time 0 —— ns tDIS DI Setup Time 50 —— ns tDIH DI Hold Time 50 —— ns tDO1 Output Delay to 1 —— 150 ns tDO0 Output Delay to 0 —— 150 ns tHZ Output Delay to High-Z — 400 — ns tBUSY Erase/Write Cycle Time — 45 ms tLZ Output Delay to Low-Z — 400 — ns tPROG Erase/Write Pulse Width 700 —— ns tPS PROG Setup Time 150 —— ns tCLKH Minimum CLK High Time 500 —— ns tCLKL Minimum CLK Low Time 300 —— ns fC Clock Frequency DC — 1 MHz Analog tDS DAC Settling Time to 1/2 LSB CLOAD = 10 pF, VDD = +5V — 310 µs CLOAD = 10 pF, VDD = +3V — 610 µs Pin Capacitance CIN Input Capacitance VIN = 0V, f = 1 MHz(2) — 8 — pF COUT Output Capacitance VOUT = 0V, f = 1 MHz(2) — 6 — pF Notes: 1. All timing measurements are defined at the point of signal crossing VDD / 2. 2. These parameters are periodically sampled and are not 100% tested. CL = 100 pF see note 1 |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
