CAT24C021J-30TE13 datasheet(9/12 Pages) CATALYST

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CAT24CXX1/XX2

Advanced

Doc. No. 25079-00 1/98 M-1

SCL

SDA

8TH BIT

STOP

NO ACK

DATA OUT

SLAVE

ADDRESS

DATA

BUS ACTIVITY:

MASTER

SDA LINE

Figure 9. Immediate Address Read Timing

Acknowledge Polling

Disabling of the inputs can be used to take advantage of

the typical write cycle time. Once the stop condition is

issued to indicate the end of the host’s write operation,

CAT24CXXX initiates the internal write cycle. ACK poll-

ing can be initiated immediately. This involves issuing

the start condition followed by the slave address for a

write operation. If CAT24CXXX is still busy with the write

operation,

ACK

will

returned.

CAT24CXXX has completed the write operation, an

ACK will be returned and the host can then proceed with

the next read or write operation.

WRITE PROTECTION

The Write Protection feature allows the user to protect

against inadvertent programming of the memory array.

If the WP pin is tied to VCC, the entire memory array is

protected and becomes read only. The CAT24CXXX

will accept both slave and byte addresses, but the

memory location accessed is protected from program-

ming by the device's failure to send an acknowledge

after the first byte of data is received.

READ OPERATIONS

The READ operation for the CAT24CXXX is initiated in

the same manner as the write operation with one excep-

tion, that R/

W bit is set to one. Three different READ

operations are possible: Immediate/Current Address

READ, Selective/Random READ and Sequential READ.

24C1601Fig.8

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