DS75LX datasheet(3/13 Pages) DALLAS

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DS75LX: Digital Thermometer and Thermostat with Extended Addressing

3 of 13

SCL Frequency

fSCL

400

kHz

AC ELECTRICAL CHARACTERISTICS (continued)

(1.7V

≤ V

DD ≤ 3.7V, TA = -55°C to +125°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Bus Free Time Between

a STOP and START

Condition

tBUF

(Note 7)

1.3

µs

START and Repeated

START Hold Time from

Falling SCL

tHD:STA

(Notes 7, 8)

600

Low Period of SCL

tLOW

(Note 7)

1.3

µs

High Period of SCL

tHIGH

(Note 7)

0.6

µs

Repeated START

Condition Setup Time to

Rising SCL

tSU:STA

(Note 7)

600

Data-Out Hold Time from

Falling SCL

tHD:DAT

(Notes 7, 9)

0.9

µs

Data-In Setup Time to

Rising SCL

tSU:DAT

(Note 7)

100

Rise Time of SDA and

SCL (Receive)

(Notes 7, 10)

20 +

0.1CB

300

Fall Time of SDA and

SCL (Receive)

(Notes 7, 10)

20 +

0.1CB

300

Spike Suppression

Filter Time (Deglitch

Filter)

tSS

STOP Setup Time to

Rising SCL

tSU:STO

(Note 7)

600

Capacitive Load for Each

Bus Line

400

Input Capacitance

Serial Interface Reset

Time

tTIMEOUT

SDA time low

(Notes 11, 12)

325

Note 1:

VDD must be decoupled with a high-quality 0.1µF bypass capacitor. X5R or X7R ceramic surface-mount capacitors are

recommended.

Note 2:

Internal heating caused by O.S. loading causes the DS75LX to read approximately 0.5

°C higher if O.S. is sinking the max

rated current.

Note 3:

All voltages are referenced to ground.

Note 4:

IDD specified with O.S. pin open and A0–A2 pins grounded.

Note 5:

IDD and address leakage specified with VDD at 3.0V and SDA, SCL = 3.0V at 0°C to +70°C.

Note 6:

Address pins A0, A1, A2 are directly connected to VDD, VSS, or floating with less than 50pF capacitive load.

Note 7:

See the timing diagram (Figure 1). All timing is referenced to 0.9 x VDD and 0.1 x VDD.

Note 8:

After this period, the first clock pulse is generated.

Note 9:

The DS75LX provides an internal hold time of at least 75ns on the SDA signal to bridge the undefined region of SCL's falling

edge.

Note 10:

For example, if CB = 300pF, then tR[min] = tF[min] = 50ns.

Note 11:

This timeout applies only when the DS75LX is holding SDA low. Other devices can hold SDA low indefinitely and the DS75LX

will not reset.

Note 12:

The DS75LX is available with timeout feature disabled upon special order. Contact Factory.

PIN DESCRIPTION

NAME

FUNCTION

SDA

Data Input/Output for 2-Wire Serial Communication Port (Open Drain)

SCL

Clock Input for 2-Wire Serial Communication Port

O.S.

Thermostat Output Open Drain

GND

Ground

Address Input

VDD

Supply Voltage. +1.7V to +3.7V supply pin. VDD must have an external bypass

capacitor to GND. 0.1µF X5R or X7R ceramic SMT caps recommended.

DS75LX Datasheet(PDF) 3 Page - Dallas Semiconductor

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