R32C111 datasheet(97/102 Pages) RENESAS

97 / 102 page

A- 4

37, 38

• Changed register names associated with “Start/Stop Condition” for

BCNiIC in Tables 4.2 and 4.3, to “Start Condition/Stop Condition”

• Modified reset values “XXXX XXXXb” and “XXXX 000Xb” for registers

U7RB and U8RB in Table 4.10, to “XXXXh”

• Changed expression of register name “Xi Register Yi Register” (i = 0 to

15) and register symbol “XiR, YiR” in Table 4.11, to “Xi Register/Yi

• Changed hexadecimal format of reset values for PDi in Table 4.16, to

binary

• Modified Note 1 in Table 4.19

• Merged addresses 40090h to 40093h in Table 4.20, into previous

page

• Modified reset values for IFS0 and IFS2 in Table 4.20; Added Notes 1

to 3 for 80-/64-pin packages and IFS7 register

55-57

• Modified the following register name in Tables 4.20 to 4.22: “Port Pi_j

Port Function Select Register”, to “Port Pi_j Function Select Register”

• Modified register name “DMAi Request Source Select Register 1” in

Table 4.24

, to “DMAi Request Source Select Register”

• Changed register names “Wake-up Interrupt Priority Level Control

Table 4.24

, to “Wake-up IPL Setting Register 2” and “Wake-up IPL

Setting Register 1”, respectively

Chapter 5. Electrical Characteristics

• Added Notes 2 and 3 for 80-/64-pin packages to Table 5.1

• Added specification of “dVCC1/dt” to Table 5.2; Added Notes 2, 4, and

5 for 80-/64-pin packages

• Added Note 2 for Table 5.3

• Added Note 3 for 80-/64-pin packages to Table 5.4

• Modified description “VCC”s in Table 5.6, to “VCC1”s and “VCC2”s

• Added Table 5.7 to provide RAM electrical characteristics

• Deleted specification of “tPS” from Table 5.8

• Deleted measurement condition for power supply circuit timing

characteristics in Table 5.9

• Added “Supply voltage for internal logic” to Figure 5.3 and deleted

“CPU clock” from the figure

• Changed voltage condition for Table 5.11, from “VCC1 = VCC2 = 3.3 to

5.5 V” to “VCC1 = VCC2 = 4.2 to 5.5 V”; Clarified maximum value for

“

Vdet” in Table 5.11; Modified self-consuming current “VCC”, to

“VCC1”

• Changed typical value and maximum value for fSO(PLL) in Table 5.12,

to “55” and “80” respectively

• Changed the following expressions: “PLL frequency synthesizer

stabilization time” in Table 5.12, to “PLL lock time” and “tOSC(PLL)”, to

“tLOCK(PLL)”

• Modified description for Note1 of Table 5.13

Revision History

R32C/111 Group Datasheet

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R32C111 Datasheet(PDF) 97 Page - Renesas Technology Corp

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