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R32C111 Datasheet(PDF) 19 Page - Renesas Technology Corp |
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R32C111 Datasheet(HTML) 19 Page - Renesas Technology Corp |
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19 / 102 page ![]() R01DS0062EJ0130 Rev.1.30 Page 19 of 93 Mar 3, 2014 R32C/111 Group 1. Overview Table 1.12 Pin Definitions and Functions for the 100-pin Package (2/4) Function Symbol I/O Power Supply Description Bus control pins A0/D0 to A7/D7 I/O VCC2 Output of address bits (A0 to A7) and input/output of data (D0 to D7) by time-division while accessing an external memory space with multiplexed bus A8/D8 to A15/D15 I/O VCC2 Output of address bits (A8 to A15) and input/ output of data (D8 to D15) by time-division while accessing an external memory space with 16-bit multiplexed bus BC0/D0 I/O VCC2 Output of byte control ( BC0) and input/output of data (D0) by time-division while accessing an external memory space with multiplexed bus CS0 to CS3 O VCC2 Chip select output WR0/WR1/WR/ BC0/BC1/RD O VCC2 Output of write, byte control, and read signals. Either WRx or WR and BCx can be selected by a program. Data is read when RD is low. • When WR0, WR1, and RD are selected, data is written to the following address: an even address, when WR0 is low an odd address, when WR1 is low on 16-bit external data bus • When WR, BC0, BC1, and RD are selected, data is written, when WR is low and the following address is accessed: an even address, when BC0 is low an odd address, when BC1 is low on 16-bit external data bus ALE O VCC2 Latch enable signal in multiplexed bus format HOLD I VCC2 The MCU is in a hold state while this pin is held low HLDA O VCC2 This pin is driven low while the MCU is held in a hold state RDY I VCC2 Bus cycle is extended by the CPU if this pin is low on the falling edge of BCLK |
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