CS3865C datasheet(6/8 Pages) CHERRY

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The error amp is compensated externally thru the VFB and

COMP pins. Its output voltage is offset by two diode

drops (≈1.4V) and divided by three before it connects to

the inverting input of the current sense comparator. This

guarantees that both outputs are disabled when the error

amplifier output is at its lowest state which occurs when

the power supply is operating at light or no-load condi-

tions, or at the beginning of a soft-start interval.

The minimum allowable error amplifier feedback resis-

tance is limited by the amplifier’s source current capability

(0.5 mA) and the output voltage (VOH) required to reach

the current sense comparator 0.5V clamp level with the

error amplifier inverting input at ground. This condition

happens during initial system start up or when the sensed

output is shorted:

RF(min) ≈

= 5800Ω

The CS3865C operates as a current mode controller.

Output switch conduction is initiated by the oscillator and

terminated when the peak inductor current reaches the

threshold level established by the error amplifier output.

Thus the error signal controls the peak inductor current on

a cycle-by-cycle basis. The current sense comparator-PWM

Latch combination ensures that only a single pulse

appears at the drive output (VOUT) during any given oscil-

lator cycle. The current is converted to a voltage by con-

necting a sense resistor RSense in series with the source of

output switch Q1 and ground. This voltage is monitored

through the Sense1,2 pins and compared to a voltage

derived from the error amp output. The peak current

under normal operating conditions is controlled by the

voltage at COMP where:

Ipk =

Abnormal operating conditions occur when the power

supply output is overloaded or if output voltage is too

high. Under these conditions, the current sense compara-

tor threshold will be internally clamped to 0.5V. Therefore

the maximum peak switch current is:

Ipk(max) =

Erratic operation due to noise pickup can result if there is

an excessive reduction of the Ipk (max) clamp voltage.

A narrow spike on the leading edge of the current wave-

form can usually be observed and may cause the power

supply to exhibit an instability when the output is lightly

loaded. The addition of an RC filter on the current sense

input reduces this spike to an acceptable level.

Two undervoltage lockout comparators have been incor-

porated to guarantee that the IC is fully functional before

the output stages are enabled. Power supply terminal

(VCC) and the reference output (VREF) are monitored by

separate comparator. Each has built-in hysteresis to pre-

vent erratic output behavior as their respective thresholds

are crossed. The upper and lower thresholds of the VCC

comparator are 14V and 10V respectively.

The VREF comparator disables the drive outputs until the

internal circuitry is functional. This comparator has upper

and lower thresholds of 3.6V and 3.4V. A 17V zener is con-

nected as a shunt regulator from VCC to ground to protect

the IC and power MOSFET gate from excessive voltage.

The guaranteed minimum operating voltage after turn-on

is 11V.

Each channel contains a single totem-pole output stage

that is specifically designed for direct drive of power

MOSFET’s. The outputs have up to ±1.0A peak current

capability and have a typical rise and fall time of 28 ns

with a 1.0nF load. Internal circuitry has been added to

keep the outputs in active pull-down mode whenever an

undervoltage lockout is active, eliminating the need for an

external pull-down resistor.

Although the outputs are optimized for MOSFET’s, they

can easily supply the negative base current required by

bipolar NPN transistors for enhanced turn-off. Since the

outputs do not contain internal current limits an external

series resistor will be required to prevent the peak output

current from exceeding the ±1.0A maximum rating. The

sink saturation (VOL) is less than 0.4V at 100mA.

A separate ground pin, Pwr Gnd, is provided. Properly

implemented, will significantly reduce the level of switch-

ing transient noise imposed on the control circuitry. This

becomes important when the Ipk(max) clamp level is

reduced.

This input is used to switch VOUT

2. VOUT1 is used to control

circuitry that runs continuously, e.g. volatile memory, the

system clock, or a remote controlled receiver. VOUT

2 out-

put can control the high power circuitry that is turned off

when not needed.

The 5.0V bandgap reference is trimmed to ±2.0% toler-

ance. The reference has short circuit protection and is

capable of sourcing 30mA for powering any additional

external circuitry.

Voltage Reference

ENABLE2

Outputs and Power Ground

Undervoltage Lockout

0.5V

RSense

V(COMP) – 1.4V

3RSense

Current Sense Comparator and PWM Latch

3 x 0.5V + 1.4V

0.5mA

Operating Description continued

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