CS7054 datasheet(5/6 Pages) CHERRY

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Application Information: continued

On Time = CFLT ´

where:

IAVG = (295.5µA ´ DC) - [4.5µA ´ (1 - DC)]

IAVG = (300µA ´ DC) - 4.5µA

DC = PWM Duty Cycle

Sleep State

This device will enter into a low current mode (<275µA)

when CTL lead is brought to less than 0.5V. All functions

are disabled in this mode, except for the regulator.

Inhibit

When the inhibit voltage is greater than 2.5V the internal

latch is set and the external MOSFET will be turned off for

the remainder of the oscillator cycle. The latch is then reset

at the start of the next cycle.

Overvoltage Shutdown

The IC will disable the output during an overvoltage

event. This is a real time fault event and does not set the

internal latch and therefore is independent of the oscillator

timing (i.e. asynchronous). There is no undervoltage lock-

out. The device will shutdown gracefully once it runs out

of headroom.

Reverse Battery

The CS7054 will not survive a reverse battery condition.

Therefore, a series diode is required between the battery

and the VCC lead.

Load Dump

VCC is internally clamped to 30V. It is recommended that a

51½ resistor, (RS) is placed in series with VCC to limit the

current flow into the IC in the event of a 40V peak tran-

sient condition.

2.4V - 0.6V

IAVG

CS7054 Datasheet(PDF) 5 Page - Cherry Semiconductor Corporation