CS8122 datasheet(5/8 Pages) CHERRY

5 / 8 page

The CS8122

function, has hysteresis on both the

reset and delay comparators, a latching Delay capacitor

discharge circuit, and operates down to 1V.

The

circuit output is an open collector type with

ON and OFF parameters as specified. The

output

NPN transistor is controlled by the two circuits described

(see Block Diagram).

The Low Voltage Inhibit Circuit monitors output voltage,

and when output voltage is below the specified minimum,

causes the

output transistor to be in the ON (satu-

ration) state. When the output voltage is above the speci-

fied level, this circuit permits the

output transistor

to go into the OFF state if allowed by the

Delay cir-

cuit.

The Reset Delay Circuit provides a programmable (by

external capacitor) delay on the

output lead. The

Delay lead provides source current to the external delay

capacitor only when the Low Voltage Inhibit circuit indi-

cates that output voltage is above VRT(ON). Otherwise, the

Delay lead sinks current to ground (used to discharge the

delay capacitor). The discharge current is latched ON

when the output voltage is below VRT(OFF). The Delay

capacitor is fully discharged anytime the output voltage

falls out of regulation, even for a short period of time. This

feature ensures that a controlled

pulse is generated

following detection of an error condition. The circuit

allows the

output transistor to go to the OFF (open)

state only when the voltage on the Delay lead is higher

than VDC(HI).

RESET

Reset Delay Circuit

RESET

Low Voltage Inhibit Circuit

RESET

VRH

VOUT

VRT(ON)

VRT(OFF)

VRL

Delay

VDC(HI)

VDC(LO)

VDH

tDelay

VDIS

(3)

(1)

(2)

RESET

(1) = No Delay Capacitor

(2) = With Delay Capacitor

(3) = Max: RESET Voltage (1.0V)

RESET Circuit Waveform

Circuit Description

Test Circuit

CIN*

100nF

VIN

Delay

Gnd

RESET

VOUT

CS8122

COUT**

RRST

4.7k

CDelay

0.1

*CIN required if regulator is far from power source filter.

**COUT required for stability.

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