CS22230 Mini PCI / USB Wireless Controller

7 of 29

DS558PP1

Rev. 1.0

www.cirrus.com

3.4

Programmable Memory Controller

The

CS22230

incorporates

a

general-purpose

memory controller

that

supports

a

SDRAM/async SRAM memory and FLASH memory interface.

In the RAM configuration, the system memory interface supports up to 16-Mbyte of 16-bit

SDRAM running at a frequency up to 103 MHz single-state access cycles or 256KB of 16 bit

async SRAM. The Memory Controller provides programming of SDRAM parameters such as

CAS latency, refresh rate, etc; these registers are located in miscellaneous configuration

registers. When there are no pending memory requests from any internal requester, the

SWG2110 will keep Clock Enable (CKE) signal low to cause the SDRAM to stay in power

down mode. Once a memory request is active, the SWG2110 will assert CKE high to cause

the SDRAM to come out of power down mode. Typically, this can reduce memory power

consumption by up to 50%.

In ROM configuration, firmware for CS22230 is stored in non-volatile memory and is

accessed through the Boot ROM interface. The maximum addressable ROM space

supported is 1MB. ROM read/write and output enable are shared with RAM control pins. The

ROM can be re-flashed allowing for software upgrades.

3.5

Mini PCI Controller Interface

Embedded in the CS22230 is a Mini PCI 2.2 fully compliant master/target 32 bit data

interface including power management support (PME signal).

The communication buffer

logic was designed to be flexible and generic to both the PC Software and ARM firmware.

Mini PCI data transfer is supported by a DMA Control Block (DCB). The DCB is configured by

the ARM, allowing the ARM to control how often it is interrupted. Mini PCI data transfers are

done by the Mini PCI master, and the DCB, offloading CPU overhead.

3.6

USB Interface

Embedded within the CS22230 is a full speed USB 1.1 compliant device interface. The

device supports from 1 to 16 endpoints and is completely programmable via firmware

download or external EEPROM.

All “setup” commands are passed to the system processor for interpretation. The device also

contains a DMA engine to transfer arbitrary amounts of data to and from main memory before

interrupting the system processor.