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CS4340 Datasheet(PDF) 20 Page - Cirrus Logic |
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CS4340 Datasheet(HTML) 20 Page - Cirrus Logic |
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20 / 28 page ![]() CS4340 20 DS297PP3 LRCK SCLK Left Channel SDATA 6543 210 7 23 22 21 20 19 18 6 543 210 7 23 22 21 20 19 18 32 clocks 0 Right Channel Internal SCLK Mode External SCLK Mode Right Justified, 24-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192 Right Justified, 24-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 48 Cycles per LRCK Period Figure 18. CS4340 Format 2 LRCK SCLK Left Channel Right Channel SDATA 6543 210 98 7 15 14 13 12 11 10 6 543 210 98 7 15 14 13 12 11 10 32 clocks Internal SCLK Mode External SCLK Mode Right Justified, 16-Bit Data INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128 INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192 Right Justified, 16-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 32 Cycles per LRCK Period Figure 19. CS4340 Format 3 |
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