CS4340A

DS590PP2

9

3.6

Power-up Sequence

Reliable power-up can be accomplished by keeping the device in reset until the power supply and config-

uration pins are stable, and the clocks are locked to the appropriate frequencies discussed in section 3.3. It

is also recommended that reset be enabled if the analog supply drops below the minimum specified oper-

ating voltage to prevent power glitch related issues.

3.7

and power-down. This technology, when used with external DC-blocking capacitors in series with the au-

dio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters.

It is activated inside the DAC when RST is enabled/disabled and requires no other external control, aside

from choosing the appropriate DC-blocking capacitors.

3.7.1

Power-up

When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to

AGND. Following a delay of approximately 1000 sample periods, each output begins to ramp to-

audio output begins. This gradual voltage ramping allows time for the external DC-blocking capac-

itors to charge to the quiescent voltage, minimizing the power-up transient.

3.7.2

Power-down

To prevent transients at power-down, the device must first enter its power-down state by enabling

RST. When this occurs, audio output ceases and the internal output buffers are disconnected from

AOUTL and AOUTR. In their place, a soft-start current sink is substituted which allows the DC-

blocking capacitors to slowly discharge. Once this charge is dissipated, the power to the device

may be turned off and the system is ready for the next power-on.

3.7.3

Discharge Time

To prevent an audio transient at the next power-on, it is necessary to ensure that the DC-blocking

capacitors have fully discharged before turning on the power or exiting the power-down state. If

not, a transient will occur when the audio outputs are initially clamped to AGND. The time that the

device must remain in the power-down state is related to the value of the DC-blocking capacitance.

For example, with a 3.3 µF capacitor, the minimum power-down time will be approximately

0.4 seconds.