CS4927 datasheet(37/56 Pages) CIRRUS

37 / 56 page

CS4923/4/5/6/7/8/9

DS262F2

6.3.1 SPI Write

When writing to the device in SPI, the same

protocol can be used for sending a byte, a word or

an entire download image as long as transfers occur

on byte boundaries. Figure 19 illustrates the

relative timing necessary for a three byte transfer to

the CS492X. The host initiates an SPI write by

driving CS low, followed by a 7-bit address and the

read/write bit set low to indicate a write. The

CS4923/4/5/6/7/8/9

internal

7-bit

address

initially assigned to 000 0000b following a reset.

The 7-bit address sent to the CS492X must match

its internal address or the incoming data will be

ignored. Address checking can be changed (either

disabled or an actual address change) if desired.

Address checking configuration is documented in

the

hardware

configuration

section

the

CS4923/4/5/6/7/8/9 Hardware User’s guide.

Data should be shifted into the CS492X most

significant bit first with data being valid at the

rising edge of SCCLK. It should be noted that data

is internally transferred to the DSP on the falling

edge of the eighth SCCLK after the eighth data bit

of a byte. For this reason SCCLK must transition

from high to low on the last bit of each byte or a

loss of data will occur. If this final transfer of

SCCLK does not occur the final byte will be lost

and successful communication will not be possible.

6.3.2 SPI Read

The CS4923/4/5/6/7/8/9 will always indicate that it

has data to be read by asserting the INTREQ line

low. The host must recognize the request and start

a read transaction with the CS492X. The same

protocol will be used whether reading a byte or

multiple bytes. Figure 19 also illustrates the

relative timing of a three byte SPI read.

The host initiates an SPI read by driving CS low,

followed by a 7-bit address and the read/write bit

set high to indicate a read. The CS492X internal 7-

bit address is initially assigned to 000 0000b

following a reset. The 7-bit address sent to the

CS492X must match its internal address or the

incoming data will be ignored. Address checking

can be disabled or the actual address can be

changed

desired.

Address

checking

configuration is documented in the hardware

configuration section of the CS4923/4/5/6/7/8/9

Hardware User’s guide.

After the address byte the host should clock data

out of the device one byte at a time until INTREQ

is no longer low. The host shifts data using the

rising edge of SCCLK. The data is valid on the

rising edge of SCCLK and transitions occur on the

falling edge. In SPI mode, the INTREQ pin is

deasserted immediately following the rising edge

of the second-to-last data bit of the current byte

being transferred if there is no more data to be read.

The INTREQ pin is guaranteed to stay deasserted

(high) until the rising edge of SCCLK for the last

data bit.

If there is more data to be read from the DSP before

the rising edge of SCCLK for the second-to-last

data bit, then INTREQ remains asserted low.

Immediately following the falling edge of SCCLK

for the last data bit of the current byte, the next data

byte loads into the internal serial shift register. The

host should continue to read this new byte. It is

important to note that once the data is in the shift

bits out of the shift register as long as CS is low.

For a thorough look at SPI communication and

critical additional comments on INTREQ behavior

reference the CS4923/4/5/6/7/8/9 Hardware User’s

Guide.

CS4927 Datasheet(PDF) 37 Page - Cirrus Logic

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