CS4927 datasheet(43/56 Pages) CIRRUS

43 / 56 page

CS4923/4/5/6/7/8/9

DS262F2

Although the memory can use more address bits,

typically only 16 bits of address space are used. For

this

reason

the

memory

example

shown

incorporates a 2 latch memory architecture.

The two latch external memory architecture is

required for the CS4926 or CS4928 when using

DTS. A three latch architecture can not be used

with the CS4926 or CS4928 running DTS since the

run time memory access uses only 2 address cycles.

6.5.1 External Memory and Autoboot

configure

the

CS4923/4/5/6/7/8/9

automatically load its code from external memory,

the ABOOT signal should be driven low at the

rising edge of RESET. Once again this mode can

only be chosen if either SPI or I2C serial

communication is being used. In serial control port

mode, holding the ABOOT pin low as the CS492X

leaves the reset state enables an automatic boot.

ABOOT can be released following the rising edge

of RESET. During the automatic boot cycle, the

serial control port should remain idle. Figure 23

shows an autoboot functional timing example.

The autoboot cycle actually is a 24 bit, or three

address byte cycle. It should be noted that for

autoboot, the most significant byte is always zero.

For this reason a two latch external memory

configuration can be used for autoboot. The higher

order address byte simply shifts out of the memory

latch and is discarded. If desired, a three latch

interface

could

also

used

with

the

CS4923/4/5/7/9 but it is not necessary.

For more information about autoboot and for a

thorough description of different external memory

architectures, reference the CS4923/4/5/6/7/8/9

Hardware User’s Guide.

RESET

ABOOT

EXTMEM

EMOE

EMWR

EMAD7:0

MA23:16

MA15:8

MA7:0

Data7:0

Figure 23. Autoboot Timing Diagram

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