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CS5101A Datasheet(PDF) 9 Page - Cirrus Logic |
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CS5101A Datasheet(HTML) 9 Page - Cirrus Logic |
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9 / 40 page  SWITCHING CHARACTERISTICS (Continued) Parameter Symbol Min Typ Max Units PDT and RBT Modes SCLK Input Pulse Period tsclk 200 - - ns SCLK Input Pulse Width Low tsclkl 50 - - ns SCLK Input Pulse Width High tsclkh 50 - - ns SCLK Input Falling to SDATA Valid tdss - 100 150 ns HOLD Falling to SDATA Valid PDT Mode tdhs - 140 230 ns TRK1, TRK2 Falling to SDATA Valid (Note 30) tdts - 65 125 ns FRN and SSC Modes SCLK Output Pulse Width Low tslkl -2tclk -tclk SCLK Output Pulse Width High tslkh -2tclk -tclk SDATA Valid Before Rising SCLK tss 2tclk-100 - - ns SDATA Valid After Rising SCLK tsh 2tclk-100 - - ns SDL Falling to 1st Rising SCLK trsclk -2tclk -ns Last Rising SCLK to SDL Rising CS5101A CS5102A trsdl trsdl - - 2tclk 2tclk 2tclk+165 2tclk+200 ns ns HOLD Falling to 1st Falling SCLK CS5101A CS5102A thfs thfs 6tclk 6tclk - - 8tclk+165 8tclk+200 ns ns CH1/2 Edge to 1st Falling SCLK tchfs -7tclk - tclk Note: 30. Only valid for TRK1, TRK2 falling when SCLK is low. If SCLK is high when TRK1, TRK2 falls, then SDATA is valid tdss time after the next falling SCLK. DIGITAL CHARACTERISTICS (TA = Tmin to Tmax; VA+, VD+ = 5V ± 10%; VA-, VD- = 5V ± 10%) Parameter Symbol Min Typ Max Units Calibration Memory Retention (Note 31) Power Supply Voltage VA+ and VD+ VMR 2.0 - - V High-Level Input Voltage VIH 2.0 - - V Low-Level Input Voltage VIL -- 0.8 V High-Level Output Voltage (Note 32) VOH (VD+)-1.0 - - V Low-Level Output Voltage IOUT = 1.6 mA VOL -- 0.4 V Input Leakage Current Iin -- 10 µA Digital Output Pin Capacitance Cout -9 - pF Notes: 31. VA- and VD- can be any value from zero to -5V for memory retention. Neither VA- or VD- should be allowed to go positive. AIN1, AIN2 or VREF must not be greater than VA+ or VD+. This parameter is guaranteed by characterization. 32. IOUT = -100 µA. This specification guarantees TTL compatibility (VOH = 2.4V @ Iout = -40 µA). CS5101A CS5102A DS45F2 9 |
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