W147 datasheet(7/12 Pages) CYPRESS

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W147G

PRELIMINARY

Serial Data Interface

The W147G features a two-pin, serial data interface that can

be used to configure internal register settings that control par-

ticular device functions.

Data Protocol

The clock driver serial protocol accepts only block writes from

the controller. The bytes must be accessed in sequential order

from lowest to highest byte with the ability to stop after any

complete byte has been transferred. Indexed bytes are not al-

lowed.

A block write begins with a slave address and a write condition.

After the command code the core logic issues a byte count

which describes how many more bytes will follow in the mes-

sage. If the host had 20 bytes to send, the first byte would be

the number 20 (14h), followed by the 20 bytes of data. The byte

count may not be 0. A block write command is allowed to trans-

fer a maximum of 32 data bytes. The slave receiver address

for W147G is 11010010. Figure 7 shows an example of a block

write.

The command code and the byte count bytes are required as

the first two bytes of any transfer. W147G expects a command

code of 0000 0000. The byte count byte is the number of ad-

ditional bytes required for the transfer, not counting the com-

mand code and byte count bytes. Additionally, the byte count

byte is required to be a minimum of 1 byte and a maximum of

32 bytes to satisfy the above requirement. Table 4 shows an

example of a possible byte count value.

A transfer is considered valid after the acknowledge bit corre-

sponding to the byte count is read by the controller. The com-

mand code and byte count bytes are ignored by the W147G.

However, these bytes must be included in the data write se-

quence to maintain proper byte allocation.

Notes:

12. The acknowledgment bit is returned by the slave/receiver (W147G).

13. Data Bytes 3 to 7 are reserved.

1 bit

7 bits

8 bits

Start bit

Slave Address

R/W

Ack

Command Code

Ack

Byte Count = N

Ack

Data Byte 1

Ack

Data Byte 2

Ack

...

Data Byte N

Ack

Stop

1 bit

8 bits

Figure 7. An Example of a Block Write[12]

Table 4. Example of Possible Byte Count Value

Byte Count Byte

Notes

MSB

LSB

0000

Not allowed. Must have at least one byte.

0000

0001

Data for functional and frequency select register (currently byte 0 in spec)

0000

0010

Reads first two bytes of data. (byte 0 then byte 1)

0000

0011

Reads first three bytes (byte 0, 1, 2 in order)

0000

0100

Reads first four bytes (byte 0, 1, 2, 3 in order)

0000

0101

Reads first five bytes (byte 0, 1, 2, 3, 4 in order)[13]

0000

0110

Reads first six bytes (byte 0, 1, 2, 3, 4, 5 in order)[13]

0000

0111

Reads first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)

0010

0000

Max byte count supported = 32

Table 5. Serial Data Interface Control Functions Summary

Control Function

Description

Common Application

Output Disable

Any individual clock output(s) can be disabled.

Disabled outputs are actively held LOW.

Unused outputs are disabled to reduce EMI and sys-

tem power. Examples are clock outputs to unused

PCI slots.

Spread Spectrum

Enabling

Enables or disables spread spectrum clocking.

For EMI reduction.

(Reserved)

Reserved function for future device revision or pro-

duction device testing.

No user application. Register bit must be written as 0.

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