W164
3
Serial Data Interface
The W164 features a two-pin, serial data interface that can be
used to configure internal register settings that control partic-
ular device functions. Upon power-up, the W164 initializes with
default register settings. Therefore, the use of this serial data
interface is optional. The serial interface is write-only (to the
clock chip) and is the dedicated function of device pins SDATA
and SCLOCK. In motherboard applications, SDATA and
SCLOCK are typically driven by two logic outputs of the
chipset. Clock device register changes are normally made
upon system initialization, if required. The interface can also
be used during system operation for power management func-
tions. Table 2 summarizes the control functions of the serial
data interface.
Operation
Data is written to the W164 in ten bytes of eight bits each.
Bytes are written in the order shown in Table 3.
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
QD
W164
VDD
Clock Load
10 k
Ω
Output
Buffer
(Load Option 1)
10 k
Ω
(Load Option 0)
Output
Low
Output Strapping Resistor
Series Termination Resistor
Figure 1. Input Logic Selection Through Resistor Load Option
Power-on
Reset
Timer
Output Three-state
Data
Latch
Hold
QD
W164
VDD
Clock Load
R
10 k
Ω
Output
Buffer
Output
Low
Output Strapping Resistor
Series Termination Resistor
Jumper Options
Resistor Value R
Figure 2. Input Logic Selection Through Jumper Option
Table 2. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled. Dis-
abled outputs are actively held LOW.
Unused outputs are disabled to reduce EMI
and system power. Examples are clock out-
puts to unused PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections beyond the
100- and 66.6-MHz selections that are provided by
the SEL100/66# pin. Frequency is changed in a
smooth and controlled fashion.
For alternate microprocessors and power
management options. Smooth frequency tran-
sition allows CPU frequency change under
normal system operation.
Output Three-state
Puts all clock outputs into a high-impedance state.
Production PCB testing.
Test Mode
All clock outputs toggle in relation to X1 input, inter-
nal PLL is bypassed. Refer to Table 4.
Production PCB testing.
(Reserved)
Reserved function for future device revision or pro-
duction device testing.
No user application. Register bit must be writ-
ten as 0.
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