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W199
PRELIMINARY
6
Writing Data Bytes
Each bit in Data Bytes 0–7 control a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit 7.
Table 5 gives the bit formats for registers located in Data Bytes
0–7.
Table 6 details additional frequency selections that are avail-
able through the serial data interface.
Table 7 details the select functions for Byte 0, bits 1 and 0.
Table 5. Data Bytes 0–7 Serial Configuration Map
Bit(s)
Affected Pin
Control Function
Bit Control
Default
Pin No.
Pin Name
0
1
Data Byte 0
7--
--
(Reserved)
--
--
0
6
--
--
SEL_2
See Table 6
0
5
--
--
SEL_1
See Table 6
0
4
--
--
SEL_0
See Table 6
0
3
--
--
Hardware/Software Frequency Select
Hardware
Software
0
2
--
--
SEL3
See Table 6
0
1–0--
--
Bit 1
Bit 0
Function (See Table 7 for function details)
0
0
Spread Spectrum Off (default)
0
1
(Reserved)
1
0
Spread Spectrum On
1
1
All Outputs Three-stated
00
Data Byte 1
7--
--
(Reserved)
--
--
0
6--
--
(Reserved)
--
--
0
5--
--
(Reserved)
--
--
0
4--
--
(Reserved)
--
--
0
3
40
SDRAM_F
Clock Output Disable
Low
Active
1
2--
--
(Reserved)
--
--
0
1
43
CPU1
Clock Output Disable
Low
Active
1
0
44
CPU_F
Clock Output Disable
Low
Active
1
Data Byte 2
7--
--
(Reserved)
--
--
0
6
7
PCI_F
Clock Output Disable
Low
Active
1
5--
--
(Reserved)
--
--
0
4
13
PCI5
Clock Output Disable
Low
Active
1
3
12
PCI4
Clock Output Disable
Low
Active
1
2
11
PCI3
Clock Output Disable
Low
Active
1
1
10
PCI2
Clock Output Disable
Low
Active
1
0
8
PCI1
Clock Output Disable
Low
Active
1
Data Byte 3
7--
--
(Reserved)
--
--
0
6--
--
(Reserved)
--
--
0
5
26
48MHz
Clock Output Disable
Low
Active
1
4
25
24MHz
Clock Output Disable
Low
Active
1
3--
--
(Reserved)
--
--
0
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