DS1215 datasheet(13/15 Pages) DALLAS

13 / 15 page

DS1215

032697 13/15

NOTES:

1. All voltages are referenced to ground.

2. Measured with load shown in Figure 6.

3. Input pulse rise and fall times equal 10 ns.

4. tWR is a function of the latter occurring edge of WE or CE in RAM mode, or OE or CE in ROM mode.

5. tDH and tDS are functions of the first occurring edge of WE or CE in RAM mode, or OE or CE in ROM mode.

6. Measured without RAM connected.

7. Trip point voltage for power–fail detect. VTP = 1.26 x VBAT. For 10% VCC= 5V + 10% operation VBAT = 3.5V max.;

for 5% operation VBAT = 3.7V max.

8. ICC01 is the maximum average load current the DS1215 can supply to memory.

9. Applies to CEO with the ROM/RAM pin grounded. When the ROM/RAM pin is connected to VCCO, CEO will go

to a low level as VCCI falls below VBAT.

10. ICC02 is the maximum average load current that the DS1215 can supply to memory in the battery backup mode.

11. Applies to all input pins except RST. RST is pulled internally to VCCI.

OUTPUT LOAD Figure 6

+5V

50 pF

680

Ω

1.1K

Ω

DS1215 Datasheet(PDF) 13 Page - Dallas Semiconductor