DS1215

032697 3/15

When the first write cycle is executed, it is compared to

bit 1 of the 64–bit comparison register. If a match is

found, the pointer increments to the next location of the

comparison register and awaits the next write cycle. If a

match is not found, the pointer does not advance and all

subsequent write cycles are ignored. If a read cycle oc-

curs at any time during pattern recognition, the present

sequence is aborted and the comparison register point-

er is reset. Pattern recognition continues for a total of 64

write cycles as described above until all the bits in the

comparison register have been matched. (This bit pat-

tern is shown in Figure 2.) With a correct match for 64

bits, the Time Chip is enabled and data transfer to or

from the timekeeping registers may proceed. The next

64 cycles will cause the Time Chip to either receive data

on D, or transmit data on Q, depending on the level of

OE pin or the WE pin. Cycles to other locations outside

the memory block can be interleaved with CEI cycles

without interrupting the pattern recognition sequence or

data transfer sequence to the Time Chip.

A 32,768 Hz quartz crystal can be directly connected to

the DS1215 via pins 1 and 2 (X1, X2). The crystal se-

lected for use should have a specified load capacitance

and crystal layout considerations, please consult

Application Note 58, “Crystal Considerations with Dal-

las Real Time Clocks”.

TIME CHIP COMPARISON REGISTER DEFINITION Figure 2

76

543

210

11

000

101

00

111

010

10

100

011

01

011

100

11

000

101

00

111

010

10

100

011

01

011

100

C5

3A

A3

5C

C5

3A

A3

5C

BYTE 0

BYTE 1

BYTE 2

BYTE 3

BYTE 4

BYTE 5

BYTE 6

BYTE 7

HEX

VALUE

NOTE:

The pattern recognition in Hex is C5, 3A, A3, 5C, C5, 3A, A3, 5C. The odds of this pattern being accidentally duplicated