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After the pattern match, the next 64 reads and/or writes are directed to the clock, and the RAM is

disabled. Once the pattern is established, the next 64 read/write cycles will be directed to the RTC

registers. When power is cycled, 64 reads should be executed prior to any writes to ensure that the RTC

registers are not written. A pattern match is ignored if the RST bit is zero and the RST pin goes low

during the match sequence. A pattern match is also terminated if a read occurs during the 64-bit match

sequence.

PATTERN MATCH—RAM

Data transfer to and from the timekeeping registers is accomplished with a serial bit stream under control

moving a pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are

access to the SmartWatch. Therefore, any address to the memory in the socket is acceptable. However,

the write cycles generated to gain access to the SmartWatch are also writing data to a location in the

mated RAM. The preferred way to manage this requirement is to set aside just one address location in

RAM as a SmartWatch scratch pad. When the first write cycle is executed, it is compared to bit 0 of the

64-bit comparison register. If a match is found, the pointer increments to the next location of the

comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance

and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition,

the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues

for 64 write cycles as described above until all the bits in the comparison register have been matched (this

bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch is enabled and data

transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the SmartWatch

pattern recognition sequence or data transfer sequence to the SmartWatch.

PATTERN MATCH—ROM

Communication with the SmartWatch is established by pattern recognition of a serial bit stream of 64 bits

that must be matched by executing 64 consecutive write cycles, placing address bit A2 low with the

proper data on address bit A0. The 64 write cycles are used only to gain access to the SmartWatch. Prior

to executing the first of 64 write cycles, a read cycle should be executed by holding A2 high. The read

cycle will reset the comparison register pointer within the SmartWatch, ensuring the pattern recognition

starts with the first bit of the sequence. When the first write cycle is executed, it is compared to bit 0 of

the 64-bit comparison register. If a match is found, the pointer increments to the next location of the

comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance

and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition,

the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues

for a total of 64 write cycles as described above, until all the bits in the comparison register have been

matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the SmartWatch is

enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause

the SmartWatch to either receive data on data in (A0) or transmit data on data out (DQ0), depending on

the level of /WRITE READ (A2).