DS1238 datasheet(2/14 Pages) DALLAS

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DS1238

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debounce circuit connected to the RST pin. An internal watchdog timer can also force the reset outputs to

the active state if the strobe input is not driven low prior to watchdog timeout. Oscillator control pins

OSCSEL and OSCIN provide either external or internal clock timing for both the reset pulse width and

the watchdog timeout period. The Watchdog Status and Reset Voltage Threshold are provided via WDS

and RVT , respectively. A block diagram of the DS1238 is shown in Figure 1.

PIN DESCRIPTION

PIN NAME

DESCRIPTION

VBAT

+3V battery input provides nonvolatile operation of control functions.

VCCO

VCC output for nonvolatile SRAM applications.

VCC

+5V primary power input.

GND

System ground.

Power-fail indicator, active high, used for external power switching as shown in

Figure 9.

RVT

Reset Voltage Threshold. Indicates that VCC is below the reset voltage threshold.

OSCIN

Oscillator input or timing capacitor. See Table 1.

OSCSEL

Oscillator Select. Selects internal or external clock functions. See Table 1.

Early warning power-fail input. This voltage sense point can be tied (via resistor

divider) to a user-selected voltage.

NMI

Non-maskable interrupt. Used in conjunction with the IN pin to indicate an impending

power failure.

Strobe input. A high-to-low transition will reset the watchdog timer, indicating that

software is still in control.

CEO

Chip enable output. Write protected. Used with nonvolatile SRAM applications.

CEI

Chip enable input.

WDS

Watchdog Status. Indicates that a watchdog timeout has occurred.

RST

Active low reset output.

RST

Active high reset output.

POWER MONITOR

The DS1238 employs a band gap voltage reference and a precision comparator to monitor the 5-volt

supply (VCC) in microprocessor-based systems. When an out-of-tolerance condition occurs, the RVT ,

RST, and RST outputs are driven to the active state. The VCC trip point (VCCTP) is set for 10% operation

so that the RVT , RST and RST outputs will become active as VCC falls below 4.5 volts (4.37 typical).

The VCCTP for the 5% operation option (DS1238-5) is set for 4.75 volts (4.62 typical). The RST and RST

signals are excellent for microprocessor reset control, as processing is stopped at the last possible moment

of in-tolerance VCC. On power up, RVT will become inactive as soon as VCC rises above VCCTP. However,

the RST and RST signals remain active for a minimum of 50 ms (100 ms typical) after VCCTP is reached

to allow the power supply and microprocessor to stabilize.

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