DS1302

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Diode and resistor selection is determined by the user according to the maximum current desired for

battery or super cap charging. The maximum charging current can be calculated as illustrated in the

~ (5.0V – 0.7V) / 2 kΩ

~ 2.2 mA

the charge current will decrease.

CLOCK/CALENDAR BURST MODE

The clock/calendar command byte specifies burst mode operation.

In this mode the first eight

clock/calendar registers can be consecutively read or written (see Figure 4) starting with bit 0 of address

0.

If the write protect bit is set high when a write clock/calendar burst mode is specified, no data transfer

will occur to any of the eight clock/calendar registers (this includes the control register). The trickle

charger is not accessible in burst mode.

At the beginning of a clock burst read, the current time is transferred to a second set of registers. The

time information is read from these secondary registers, while the clock may continue to run. This

eliminates the need to re-read the registers in case of an update of the main registers during a read.

RAM

The static RAM is 31 x 8 bytes addressed consecutively in the RAM address space.

RAM BURST MODE

The RAM command byte specifies burst mode operation. In this mode, the 31 RAM registers can be

consecutively read or written (see Figure 4) starting with bit 0 of address 0.

REGISTER SUMMARY

A register data format summary is shown in Figure 4.

CRYSTAL SELECTION

A 32.768 kHz crystal can be directly connected to the DS1302 via X1 and X2. The crystal selected for

use should have a specified load capacitance (CL) of 6 pF. For more information on crystal selection and

crystal layout consideration, please consult Application Note 58, “Crystal Considerations with Dallas

Real Time Clocks."