DS1395 datasheet(3/19 Pages) DALLAS

3 / 19 page

DS1395/DS1397

020794 3/19

ADDITIONAL PIN DESCRIPTION

(FOR DS1395, DS1395S)

X1, X2 – Connections for a standard 32.768 KHz quartz

crystal, Daiwa part number DT-26S or equivalent. The

internal oscillator circuitry is designed for operation with

a crystal having a specified load capacitance (CL) of

6 pF. The crystal is connected directly to the X1 and X2

pins. There is no need for external capacitors or resis-

tors. Note: X1 and X2 are very high impedance nodes.

It is recommended that they and the crystal be guard–

ringed with ground and that high frequency signals be

kept away from the crystal area. For more information

on crystal selection and crystal layout considerations,

please consult Application Note 58, “Crystal Consider-

ations with Dallas Real Time Clocks”.

VBAT – Battery input for any standard +3 volt lithium cell

or other energy source. Battery voltage must be held

between 2.5 and 3.5 volts for proper operation. The

nominal write protect trip point voltage at which access

to the real time clock and user RAM is denied is set by

the internal circuitry as 1.26 x VBAT. A maximum load of

µA at 25oC and 3.0V on VBAT in the absence of power

should be used to size the external energy source.

The battery should be connected directly to the VBAT

pin. A diode must not be placed in series with the battery

to the VBAT pin. Furthermore, a diode is not necessary

because reverse charging current protection circuitry is

provided internal to the device and has passed the

requirements of Underwriters Laboratories for UL list-

ing.

BGND – Battery ground: This pin or pin 14 can be used

for the battery ground return.

OPERATION

Power-Down/Power-Up: The real time clock will con-

tinue to operate and all of the RAM, time, and calendar

and alarm memory locations will remain non-volatile re-

gardless of the voltage level of VDD. When the voltage

level applied to the VDD input is greater than 4.25 volts

(typical), the module becomes accessible after 200 ms

provided that the oscillator and countdown chain have

been programmed to be running. This time period al-

lows the module to stabilize after power is applied.

When VDD falls below the CETHR (4.25 volts typical), the

chip select inputs RTC and XRAM are forced to an inac-

tive state regardless of the state of the pin signals. This

puts the module into a write protected mode in which all

inputs are ignored and all outputs are in a high imped-

ance state. When VDD falls below 3.2 volts (typical), the

module is switched over to an internal power source in

the case of the DS1397, or to an external battery con-

nected to the VBAT and BGND pins in the case of the

DS1395 and DS1395S, so that power is not interrupted

to timekeeping and nonvolatile RAM functions.

Address Map: The registers of the device appear in two

distinct address ranges. One set of registers is active

when RTC is asserted low and represents the real time

clock. The second set of registers is active when XRAM

is asserted low and represents the extended RAM.

RTC Address Map: The address map of the RTC mod-

ule is shown in Figure 2. The address map consists of

50 bytes of general purpose RAM, 10 bytes of RTC/cal-

endar information, and 4 bytes of status and control in-

formation. All 64 bytes can be accessed as read/write

registers except for the following:

1. Registers C and D are Read Only (status informa-

tion)

2. Bit 7 of register A is Read Only

3. Bit 7 of the ”Seconds” byte (00) is Read Only

The first byte of the real time clock address map is the

RTC indirect address register, accessible when A0 is

low. The second byte is the RTC data register, accessi-

ble when A0 is high. The function of the RTC indirect ad-

dress register is to point to one of the 64 RTC registers

that are indirectly accessible through the RTC data reg-

ister.

Extended RAM Address Map: The first 32 bytes of the

extended RAM represent one of 128 pages of general

purpose nonvolatile memory. These 32 bytes on a page

are addressed by A0 through A4 when A5 is low. When

A5 is high, the XRAM page register is accessible. The

value in the XRAM page register points to one of 128

pages of nonvolatile memory available. The address of

the XRAM page register is dependent only on A5 being

high; thus, there are 31 aliases of this register in I/0

spaces. (See Figure 3.)

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