DS1743/DS1743P

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DS1743 BLOCK DIAGRAM Figure 1

DS1743 TRUTH TABLE Table 1

CE

CE2

OE

WE

MODE

DQ

POWER

X

X

X

DESELECT

HIGH-Z

STANDBY

X

X

DESELECT

HIGH-Z

STANDBY

WRITE

DATA IN

ACTIVE

READ

DATA OUT

ACTIVE

READ

HIGH-Z

ACTIVE

X

X

X

X

DESELECT

HIGH-Z

CMOS STANDBY

X

X

X

X

DESELECT

HIGH-Z

DATA RETENTION

MODE

SETTING THE CLOCK

As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read

bit, halts updates to the DS1743 registers. The user can then load them with the correct day, date and time

data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock

counters and allows normal operation to resume.

STOPPING AND STARTING THE CLOCK OSCILLATOR

The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off

Table 2. Setting it to a 1 stops the oscillator.

FREQUENCY TEST BIT

As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to

logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the

seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for

stable).