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DS9034PCX Datasheet(PDF) 4 Page - Dallas Semiconductor

Part # DS9034PCX
Description  Y2KC Nonvolatile Timekeeping RAM
PDF  17 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS9034PCX Datasheet(HTML) 4 Page - Dallas Semiconductor

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DS1743/DS1743P
4 of 17
CLOCK ACCURACY (DIP MODULE)
The DS1743 is guaranteed to keep time accuracy to within
±1 minute per month at 25°C. The RTC is
calibrated at the factory by Dallas Semiconductor using nonvolatile tuning elements, and does not require
additional For this reason, methods of field clock calibration are not available and not necessary.
Clock
accuracy is also effected by the electrical environment and caution should be taken to place the RTC in the
lowest level EMI section of the PCB layout. For additional information please see application note 58.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1743 and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within
±1.53 minutes per month (35 ppm) at 25°C. Clock
accuracy is also effected by the electrical environment and caution should be taken to place the RTC in the
lowest level EMI section of the PCB layout. For additional information please see application note 58.
DS1743 REGISTER MAP Table 2
DATA
ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
FUNCTION/RANGE
1FFF
10 Year
YEAR
YEAR
00-99
1FFE
X
X
X
10 Mo
MONTH
MONTH
01-12
1FFD
X
X
10 Date
DATE
DATE
01-31
1FFC
BF
FT
X
X
X
DAY
DAY
01-07
1FFB
X
X
10 HOUR
HOUR
HOUR
00-23
1FFA
X
10 MINUTES
MINUTES
MINUTES
00-59
1FF9
OSC
10 SECONDS
SECONDS
SECONDS
00-59
1FF8
W
R
10 CENTURY
CENTURY
CONTROL
00-39
OSC
= STOP BIT
R = READ BIT
FT = FREQUENCY TEST
W = WRITE BIT
X = SEE NOTE BELOW
BF = BATTERY FLAG
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1743 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE
(chip enable) is low. The device architecture allows ripple-through access to any of the address locations
in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is
stable, providing that the CE , and OE access times and states are satisfied. If CE , or OE access times and
states are not met, valid data will be available at the latter of chip enable access (tCEA) or at output enable
access time (tCEA). The state of the data input/output pins (DQ) is controlled by CE , and OE . If the
outputs are activated before tAA, the data lines are driven to an intermediate state until tAA. If the address
inputs are changed while CE , and OE remain valid, output data will remain valid for output data hold time
(tOH) but will then go indeterminate until the next address access.



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