+2.7V, Low-Power, Multichannel,

Serial 8-Bit ADCs

_______________________________________________________________________________________

5

TIMING CHARACTERISTICS (Figures 8 and 9)

Note 1:

Relative accuracy is the analog value’s deviation (at any code) from its theoretical value after the full-scale range is calibrated.

Note 2:

See

Typical Operating Characteristics.

Note 3:

Note 4:

On-channel grounded; sine wave applied to all off-channels.

Note 5:

Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.

Note 6:

Guaranteed by design. Not subject to production testing.

Note 7:

Note 8:

External load should not change during the conversion for specified accuracy.

Note 9:

External reference at 2.048V, full-scale input, 500kHz external clock.

Note 10: Measured as

Note 11: 1µF at REFOUT; internal reference settling to 0.5 LSB.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Track/Hold Acquisition Time

1µs

DIN to SCLK Setup

100

ns

DIN to SCLK Hold

0ns

SCLK Fall to Output Data Valid

20

200

ns

CS Fall to Output Enable

240

ns

CS Rise to Output Disable

240

ns

CS to SCLK Rise Setup

100

ns

CS to SCLK Rise Hold

0ns

SCLK Pulse Width High

200

ns

SCLK Pulse Width Low

200

ns

SCLK Fall to SSTRB

240

ns

CS Fall to SSTRB Output Enable

(Note 6)

Figure 1, external clock mode only,

240

ns

CS Rise to SSTRB output

Disable (Note 6)

Figure 2, external clock mode only,

240

ns

SSTRB Rise to SCLK Rise

(Note 6)

Figure 11, internal clock mode only

0

ns

External reference

20

µs

Wake-Up Time

Internal reference (Note 11)

12

ms