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DS9101 Datasheet(PDF) 12 Page - Dallas Semiconductor |
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DS9101 Datasheet(HTML) 12 Page - Dallas Semiconductor |
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12 / 12 page ![]() DS1904 12 of 12 NOTES: 1. All voltages are referenced to ground. 2. VPUP = external pull-up voltage. 3. Input load is to ground. 4. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 1 µs of this falling edge. 5. Under certain low voltage conditions VIL1MAX may have to be reduced to as much as 0.5V to always guarantee a presence pulse. 6. The reset low time (tRSTL) should be restricted to a maximum of 960 µs, to allow interrupt signaling, otherwise, it could mask or conceal interrupt pulses. 7. The master must read while the data is valid. |
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