DS21372

5 of 21

PIN

SYMBOL

TYPE

DESCRIPTION

24

RL

I

Receive Load. A positive-going edge loads the previous 32 bits of data

received at RDATA into the Pattern Receive Registers. RL is logically

25

RDATA

I

Receive Data. Received NRZ serial data, sampled on the rising edge of

RCLK.

26

RDIS

I

Receive Disable. Set high to prevent the data at RDATA from being

sampled. Set low to allow bits at RDATA to be sampled. Should be tied

operations are disabled when RDIS is high.

27

RCLK

I

Receive Clock. Input clock from transmission link. 0 to 20 MHz. Can

be a gapped clock. Fully independent from TCLK.

28

-

Positive Supply. 3.3 volts.

29

-

Signal Ground. 0.0 volts. Should be tied to local ground plane.

30

TCLK

I

Transmit Clock.

Transmit demand clock. 0 to 20 MHz. Can be a

gapped clock. Fully independent of RCLK.

31

TDIS

I

Transmit Disable. Set high to hold the current bit being transmitted at

TDATA. Set low to allow the next bit to appear at TDATA. Should be

side operations are disabled when TDIS is high.

32

TDATA

O

Transmit Data. Transmit NRZ serial data, updated on the rising edge of

TCLK.

DS21372 REGISTER MAP Table 2

ADDRESS

R/W

REGISTER NAME

ADDRESS

R/W

REGISTER NAME

00

R/W

Pattern Set Register 3.

0C

R

Bit Error Counter Register 3.

01

R/W

Pattern Set Register 2.

0D

R

Bit Error Counter Register 2.

02

R/W

Pattern Set Register 1.

0E

R

Bit Error Counter Register 1.

03

R/W

Pattern Set Register 0.

0F

R

Bit Error Counter Register 0.

04

R/W

Pattern Length Register.

10

R

Pattern Receive Register 3.

05

R/W

Polynomial Tap Register.

11

R

Pattern Receive Register 2.

06

R/W

Pattern Control Register.

12

R

Pattern Receive Register 1.

07

R/W

Error Insert Register.

13

R

Pattern Receive Register 0.

08

R

Bit Counter Register 3.

14

R

Status Register.

09

R

Bit Counter Register 2.

15

R/W

Interrupt Mask Register.

0A

R

Bit Counter Register 1.

1C

R/W

Test Register (see note 1)

0B

R

Bit Counter Register 0.

NOTE:

1. The Test Register must be set to 00 hex to insure proper operation of the DS21372.