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DS21FF42 Datasheet(PDF) 98 Page - Dallas Semiconductor |
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DS21FF42 Datasheet(HTML) 98 Page - Dallas Semiconductor |
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98 / 145 page  DALLAS SEMICONDUCTOR DS21FF42/DS21FT42 101899 /123 98 23.2 TAP Controller State Machine This section covers the details on the operation of the Test Access Port (TAP) Controller State Machine. Please see Figure 23.2 for details on each of the states described below. TAP Controller The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. Test-Logic-Reset Upon power up of the DS21Q42, the TAP Controller will be in the Test-Logic-Reset state. The Instruction register will contain the IDCODE instruction. All system logic of the DS21Q42 will operate normally. Run-Test-Idle The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and Test registers will remain idle. Select-DR-Scan All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the controller into the Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on JTCLK moves the controller to the Select-IR Capture-DR +V Boundary Scan Register Identification Register Bypass Register Instruction Register JTDI JTMS JTCLK JTRST JTDO +V +V Test Access Port Controller MUX 10K 10K 10K Select Output Enable |
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