DS89C420 datasheet(2/59 Pages) DALLAS

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DS89C420

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FEATURES

§ 80C52 compatible

- 8051 pin and instruction-set compatible

- Four bidirectional I/O ports

- Three 16-bit timer counters

- 256 bytes scratchpad RAM

§ On-chip memory

- 16kB flash memory

- In-system programmable through serial

port

- 1kB SRAM for MOVX

§ ROMSIZE feature

- Selects internal program memory size from

0 to 16k

- Allows access to entire external memory

map

- Dynamically adjustable by software

§ High-speed architecture

- 1 clock-per-machine cycle

- DC to 33MHz operation

- Single-cycle instruction in 30ns

- Optional variable length MOVX to access

fast/slow peripherals

- Dual data pointers with auto

increment/decrement and toggle select

- Supports four paged modes

§ Power Management Mode

- Programmable clock divider

- Automatic hardware and software exit

§ Two full-duplex serial ports

§ Programmable watchdog timer

§ 13 interrupt sources (six external)

§ Five levels of interrupt priority

§ Power-fail reset

§ Early warning power-fail interrupt

DETAILED DESCRIPTION

The DS89C420 is pin compatible with all three packages of the standard 8051 and includes standard

resources such as three timer/counters, four 8-bit I/O ports, and a serial port. It features 16kB of in-system

programmable flash memory, which can be programmed in-system from an I/O port using a built-in

program memory loader. It can also be loaded externally using standard commercially available

programmers.

Besides greater speed, the DS89C420 includes 1kB of data RAM, a second full-hardware serial port,

seven additional interrupts, two more levels of interrupt priority, programmable watchdog timer, brown-

out monitor, and power-fail reset. The device also provides dual data pointers (DPTRs) to speed up

block-data memory moves. This feature is further enhanced with a new selectable automatic

increment/decrement and toggle-select operation. The speed of MOVX data memory access can be

adjusted by adding stretch values up to 10 machine cycle times for flexibility in selecting external

memory and peripherals.

A power management mode (PMM) significantly consumes less power by slowing the CPU execution

rate from 1 clock period per cycle to 1024 clock periods per cycle. A selectable switchback feature can

automatically cancel this mode to enable a normal speed response to interrupts.

The EMI reduction feature disables the ALE signal when the processor is not accessing external memory.

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