HD64F36024FX datasheet(21/386 Pages) RENESAS

21 / 386 page

Rev. 4.00 Sep. 23, 2005 Page xix of xxvi

Figure 11.7 Input Capture Operating Example........................................................................... 151

Figure 11.8 Buffer Operation Example (Input Capture)............................................................. 152

Figure 11.9 PWM Mode Example (1) ........................................................................................ 153

Figure 11.10 PWM Mode Example (2) ...................................................................................... 154

Figure 11.11 Buffer Operation Example (Output Compare) ...................................................... 155

Figure 11.12 PWM Mode Example

(TOB, TOC, and TOD = 0: initial output values are set to 0) ............................... 156

Figure 11.13 PWM Mode Example

(TOB, TOC, and TOD = 1: initial output values are set to 1) ............................... 157

Figure 11.14 Count Timing for Internal Clock Source............................................................... 158

Figure 11.15 Count Timing for External Clock Source.............................................................. 158

Figure 11.16 Output Compare Output Timing ........................................................................... 159

Figure 11.17 Input Capture Input Signal Timing........................................................................ 160

Figure 11.18 Timing of Counter Clearing by Compare Match................................................... 160

Figure 11.19 Buffer Operation Timing (Compare Match).......................................................... 161

Figure 11.20 Buffer Operation Timing (Input Capture) ............................................................. 161

Figure 11.21 Timing of IMFA to IMFD Flag Setting at Compare Match .................................. 162

Figure 11.22 Timing of IMFA to IMFD Flag Setting at Input Capture...................................... 162

Figure 11.23 Timing of Status Flag Clearing by CPU................................................................ 163

Figure 11.24 Contention between TCNT Write and Clear ......................................................... 164

Figure 11.25 Internal Clock Switching and TCNT Operation.................................................... 164

Figure 11.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at the

Same Timing ......................................................................................................... 165

Section 12 Watchdog Timer

Figure 12.1 Block Diagram of Watchdog Timer ........................................................................ 167

Figure 12.2 Watchdog Timer Operation Example...................................................................... 171

Section 13 Serial Communication Interface 3 (SCI3)

Figure 13.1 Block Diagram of SCI3........................................................................................... 176

Figure 13.2 Data Format in Asynchronous Communication ...................................................... 192

Figure 13.3 Relationship between Output Clock and Transfer Data Phase

(Asynchronous Mode)(Example with 8-Bit Data, Parity, Two Stop Bits) .............. 192

Figure 13.4 Sample SCI3 Initialization Flowchart ..................................................................... 193

Figure 13.5 Example of SCI3 Transmission in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit) ........................................................................... 194

Figure 13.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode)...................... 195

Figure 13.7 Example of SCI3 Reception in Asynchronous Mode

(8-Bit Data, Parity, One Stop Bit) ........................................................................... 196

Figure 13.8 Sample Serial Reception Data Flowchart (Asynchronous Mode)(1)....................... 198

Figure 13.8 Sample Serial Reception Data Flowchart (Asynchronous Mode)(2)....................... 199

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