ZADCS146/147

12-Bit, 200ksps, ADC Family

Data Sheet

October 12, 2011

© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without

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Hardware Power Down

The third power down mode is called Hardware Power-Down. It is initiated by pulling the nSHDN pin LOW. If

this condition is true, the device will immediately shut down all circuitry just as in Full Power Down-Mode.

The IC wakes up if nSHDN is tied HIGH. There is no internal pull-up that would allow nSHDN to float during

normal operation. This ensures the lowest possible power consumption in power down mode.

General Power Considerations

Even without activating any power down mode, the ZADCS146 and ZADCS147 reduce their power

consumption between conversions automatically. The comparator, which contributes a considerable amount

to the overall current consumption of the device, is shut off as soon as a conversion is ended. It gets turned on

at the start of the next acquisition period. This explains the difference between the IDDstatic and IDDactive

measurements shown in chapter 1.4 Typical Operating Characteristics.

The average current consumption of the device depends very much on the sampling frequency and the type

of protocol used to communicate with the device.

In order to achieve the lowest power consumption at low sampling frequencies, it is suggested to keep the

conversion clock frequency at the maximum level of 3.2MHz and to power down the device between

consecutive conversions. Figure 16 shows the characteristic current consumption of the ZADCS147 with

external reference supply versus Sampling Rate