Micrel, Inc.

MIC2782

February 21, 2014

3

Revision 2.0

Chip Scale Package (CS) Bump Configuration

Y = Year Code

WW = Week Code

TOP VIEW

TOP VIEW (BUMP SIDE DOWN)

BOTTOM VIEW (BUMP SIDE UP)

6-Bump, 0.4mm pitch, 0.8mm x 1.2mm WLCSP

Pin Description

Bump

Designation

Bump

Name

Pin Function

A1

ANDOUT

NMOS Open-Drain output, Active-Low. Asserts low 1.5ms after /MR1 and /MR2 are both asserted

low. Connect a resistor greater than 5k

Ω from the ANDOUT pin to VDD in order to pull up the

ANDOUT output voltage when inactive. No ESD diode from ANDOUT to VDD. Please see the

Functional Description and Timing Diagram sections for further details of how the ANDOUT

output functions.

A2

/MR2

Manual Reset Input 2, Active-Low. Internal 65k

Ω (typical) Pull-Up Resistor to VDD. Pulling both

manual reset inputs low for longer than the setup period causes one RESET output pulse for the

reset timeout delay period.

B1

RESET

NMOS Open-Drain output, Active-Low. Asserts low after /MR1 and /MR2 have both asserted low

for longer than setup period. Connect a resistor greater than 5k

Ω from the RESET pin to VDD in

order to pull up the RESET output voltage when inactive. No ESD diode from RESET to VDD.

Please see the Functional Description and Timing Diagram sections for further details of how the

RESET output functions.

B2

/MR1

Manual Reset Input 1, Active-Low. Internal 65k

Ω (typical) Pull-Up Resistor to VDD. Pulling both

manual reset inputs low for longer than the setup period causes one RESET output pulse for the

reset timeout delay period.

C1

VDD

Supply Voltage. Bypass to ground with minimum 0.1µF capacitor.

C2

GND

Supply Ground.