PI6C48543 datasheet(1/7 Pages) PERICOM

Part #	PI6C48543

Description	3.3V Low Skew 1-to-4, 800MHz, Differential to LVDS Fanout Buffer

PDF	7 Pages

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Manufacturer	PERICOM [Pericom Semiconductor Corporation]

Direct Link	http://www.pericom.com

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1 / 7 page

1

PS8771B

10/02/08

PI6C48543

Block Diagram

Features

•

Maximum operation frequency: 800 MHz

•

4 pair of differential LVDS outputs

•

Selectable differential CLK and PCLK inputs

•

CLK, nCLK pair accepts LVDS, LVPECL, LVHSTL, SSTL

and HCSL input level

•

PCLK, nPCLK pair supports LVPECL, CML and SSTL

input level

•

Output Skew: 40ps (maximum)

•

Part-to-part skew: 300ps (maximum)

•

Propagation delay: 2.2ns (maximum)

•

3.3V power supply

•

Pin-to-pin compatible to ICS8543

•

Operating Temperature: -40oC to 85oC

•

Packaging (Pb-free & Green):

-20-pin TSSOP (L)

3.3V Low Skew 1-to-4, 800MHz,

Differential to LVDS Fanout Buffer

Description

The PI6C48543 is a high-performance low-skew LVDS fanout

buffer. PI6C48543 features two selectable differential inputs and

translates to four LVDS outputs. The inputs can also be conﬁgured

to single-ended with external resistor bias circuit. The CLK input

accepts LPECL or LVDS or LVHSTL or SSTL or HCSL signals,

and PCLK input accepts LVPECL or SSTL or CML signals. The

outputs are synchronized with input clock during asynchronous

assertion/deassertion of CLK_EN pin. PI6C48543 is ideal for

differential to LVDS translations and/or LVDS clock distribution.

Typical clock translation and distribution applications are data-

communications and telecommunications.

Pin Diagram

Q0

nQ0

VCC

Q1

nQ1

Q2

nQ2

GND

Q3

nQ3

GND

CLK_EN

CLK_SEL

CLK

nCLK

PCLK

nPCLK

OE

GND

VCC

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

CLK_EN

CLK

nCLK

PCLK

nPCLK

CLK_SEL

OE

Q0

nQ0

Q1

nQ1

Q2

nQ2

Q3

nQ3

0

1

D

LE

Q

08-0247

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PI6C48543 Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation

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