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HM5259165B Datasheet(PDF) 24 Page - Elpida Memory

Part # HM5259165B
Description  512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 횞 16-bit 횞 4-bank/16-Mword 횞 8-bit 횞 4-bank /32-Mword 횞 4-bit 횞 4-bank PC/133, PC/100 SDRAM
PDF  63 Pages
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Manufacturer  ELPIDA [Elpida Memory]
Direct Link  http://www.elpida.com/en
Logo ELPIDA - Elpida Memory

HM5259165B Datasheet(HTML) 24 Page - Elpida Memory

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HM5259165B/HM5259805B/HM5259405B-75/A6
Data Sheet E0118H10
24
Write operation: Burst write or single write mode is selected by the OPCODE (BA1, BA0, A12, A11, A10,
A9, A8) of the mode register.
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write
starts in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can
be set to 1, 2, 4 and 8, like burst read operations. The write start address is specified by the column address
and the bank select address (BA0/BA1) at the write command set cycle.
WRIT
CLK
Command
Din
ACTV
Row
Column
in 0
in 6
in 7
Address
in 1
in 4
in 5
in 3
BL = 1
BL = 2
BL = 4
BL = 8
t RCD
in 0
in 0
in 0
in 1
in 1
in 2
in 2
in 3
CAS Latency = 2, 3
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write
operation, data is only written to the column address and the bank select address (BA0/BA1) specified by the
write command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).
WRIT
CLK
Command
Din
ACTV
Row
Column
in 0
Address
t RCD



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