HM5259165B datasheet(39/63 Pages) ELPIDA

Part #	HM5259165B

Description	512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword 횞 16-bit 횞 4-bank/16-Mword 횞 8-bit 횞 4-bank /32-Mword 횞 4-bit 횞 4-bank PC/133, PC/100 SDRAM

PDF	63 Pages

Scroll/Zoom	100%

Manufacturer	ELPIDA [Elpida Memory]

Direct Link	http://www.elpida.com/en

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39 / 63 page

HM5259165B/HM5259805B/HM5259405B-75/A6

Data Sheet E0118H10

DQM Control

The DQM mask the DQ data. The DQMU and DQML mask the upper and lower bytes of the DQ data,

respectively. The timing of DQMU/DQML is different during reading and writing.

Reading: When data is read, the output buffer can be controlled by DQM, DQMU/DQML. By setting

DQM, DQMU/DQML to Low, the output buffer becomes Low-Z, enabling data output. By setting DQM,

DQMU/DQML to High, the output buffer becomes High-Z, and the corresponding data is not output.

However, internal reading operations continue. The latency of DQM, DQMU/DQML during reading is 2

clocks.

Writing: Input data can be masked by DQM, DQMU/DQML. By setting DQM, DQMU/DQML to Low,

data can be written. In addition, when DQM, DQMU/DQML is set to High, the corresponding data is not

written, and the previous data is held. The latency of DQM, DQMU/DQML during writing is 0 clock.

Reading

CLK

DQ (output)

out 0

out 1

= 2 Latency

out 3

DOD

DQM,

DQMU/DQML

High-Z

Writing

CLK

DQ (input)

in 0

in 1

= 0 Latency

in 3

DID

DQM,

DQMU/DQML

HM5259165B Datasheet(PDF) 39 Page - Elpida Memory