PBL38582SLASH1SOS datasheet(6/9 Pages) ERICSSON

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PBL 385 82

100

120

V line

V telephone line

V pin 4

V pin 2

Figure 7. DC - characteristics.( R6 = 75

Ω )

Transmitter amplifier

The transmitter amplifier in PBL38582

consists of three stages. The first stage is

an amplitude limiter for the input signal at

TI, in order to prevent the transmitted sig-

nal to exceed a certain set level and cause

distortion. The second stage amplifies

further the signal from the first and adds it

to a DC level from an internal DC-regulation

loop in order to give the required DC

characteristic to the telephone set. The

output of this stage is TO. The third stage

is a current generator that presents a high

impedance towards the line and has its

gain from TO

to +L. The gain of this

amplifier is ZL/R6 where ZL is the

impedance across the telephone line.

Hence, the absolute maximum signal

amplitude that can be transmitted to the

line undistorted is dependent of R6.

(amplitude limiting)

The transmitter gain is

set by the

analog (transmitter) signal from the pass-

band circuit and the frequency response is

set by the capacitors at input circuit at pin

3, the low end being influenced by C3 and

the high end by C6.

The input signal

source impedance to the transmitter

amplifier input TI should be reasonably low

in order to keep the gain spread down.

Receiver amplifier

The receiver amplifier consists of three

stages, the first stage being an input buffer

that renders the input a high impedance.

The second stage is a gain regulated diffe-

rential amplifier and the third stage a

balanced power amplifier. The power

amplifier has a differential output with low

DC- offset voltage, therefore a series

capacitor with the load is normally not

necessary. The receiver amplifier uses at

max. swing 4-6 mA peak. This current is

drawn from the +Line. The gain and

frequency response is set at the input RI

with a RC-network. The receiver gain can

be regulated.The range of regulation from

the input to the output is 5

± 2 dB (19 to

24dB). The balanced earphone amplifie

can not be loaded to full (both current and

signal level ) single ended.The signal would

be distorded when returned to ground.

A methode is shown in fig.8

how to

connect a light load (5k ac. or DC wise) to

the output. It is preferred that both outputs

are loaded the same. The receiver has, as

a principal protection, two series diodes

anti parallel across its output to limit the

signal to the earphone and thus preventing

an acoustical shock. A resistor in series

with the output can very well be used to

increase the protection level. Note, that

the noise in the receiver is allways trans-

mitter noise that has been more or less

well balanced out by the side tone network.

The RC - network (optional) at the

output is to stabilize against the inductive

load that an earphone represents.

Gain regulation.

The receiver is gain regulated (line

loss compensated).

There is a fixed default compensation

on the chip that can be adjusted or or set to

constant high or low gain mode. The input

impedance at the gain regulation pin 6 is

5.5k

± 20%. The default regulation pattern

is valid when the input is left open. Fig. 9

shows a typical receiver gain pattern ver-

sus line length. The following will show,

what to alter, to change the look of the

curve.

a). Adjustable with R12 for the recei-

ver.

b). The attack point of the regulator-

can be adjusted with resistors R13 or R14

to either direction, up or down, on the line

current axis.

c). The angle of elevation of the curve

is mainly set by the value of R6. If the DC-

characteristics is set according to the line

parameters and a correct value for R6 is

chosen the angle is mostly correct but it

can be adjusted with R6. The adjustement

will affect the DC-characteristics as well as

most of the other parameters. This is why

the DC- characteristic is set early in the

design phase.

Figure 8. Unbalanced Rx loading.

PBL 38 582

Z > 5k

The capacitor C is optional

(C)

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