8

www.pericom.com

P-0.1

10/12/2011

PI6C20400B

1:4 Clock Driver for Intel PCIe® 3.0 Chipsets

Symbol

Parameters

Condition

Min

Typ.

Max.

Units

Notes

F

IN

PLL Mode

95

105

MHz

Bypass Mode

100

400

MHz

T

Rise and Fall Time (measured be-

tween 0.175V to 0.525V)

175

700

ps

2

DT

Rise and Fall Time Variation

125

ps

2

T

pd

PLL Mode

±250

ps

Non-PLL Mode

2.5

6.5

ns

T

jitter

Cycle – Cycle Jitter

50

ps

3, 4

V

HIGH

Voltage High including overshoot

660

1150

mV

2

V

LOW

Voltage Low including undershoot

-300

mV

2

V

cross

Absolute crossing point voltages

250

550

mV

2

DV

cross

Total Variation of Vcross over all

edges

140

mV

2

T

DC

Duty Cycle

45

55

%

3

t

jphPCIeG1

Phase Jitter, PLL Mode

PCIe Gen1

30

86

ps (p-p)

t

jphPCIeG2

PCIE_2_0_8MHz_1_5M_H3_STEP,

Low Freq.

0.7

3

ps (rms)

PCIE_2_0_8MHz_1_5M_H3_STEP,

High Freq.

2

3.1

t

jphPCIeG3

PCIE_3_0_2MHz_5M_H3_FIRST,

Low Freq.

2

3

PCIE_3_0_2MHz_5M_H3_FIRST,

High Freq.

0.47

1

t

jphPCIeG1

Additive Phase Jitter, Bypass Mode

PCIe Gen1

0

0.001

ps (p-p)

t

jphPCIeG2

PCIE_2_0_8MHz_1_5M_H3_

FIRST, Low Freq.

0

0.001

ps (rms)

PCIE_2_0_8MHz_1_5M_H3_

FIRST, High Freq.

0

0.001

t

jphPCIeG3

PCIE_3_0_2MHz_5M_H3_FIRST,

Low Freq.

0

0.001

PCIE_3_0_2MHz_5M_H3_FIRST,

High Freq.

0

0.001

Notes:

1. Test configuration is R

2. Measurement taken from Single Ended waveform.

3. Measurement taken from Differential waveform.

4. Measurement taken using M1 data capture analysis tool.

5. Additive jitter is calculated from input and output RMS phase jitter by using PCIe 2.0 filter. (T

2

11-0126