LM3485EVAL datasheet(13/22 Pages) TI

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LM3485

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SNVS178F – MAY 2004 – REVISED SEPTEMBER 2009

Using the minimum value for ICL_ADJ (3.0µA) ensures that the current limit threshold will be set higher than the

peak inductor current.

The RADJ value must be selected to ensure that the voltage at the ADJ pin does not fall below 3.5V. With this in

mind, RADJ_MAX = (VIN-3.5)/7µA. If a larger RADJ value is needed to set the desired current limit, either use a

PFET with a lower RDSON, or use a current sense resistor as shown in Figure 6.

The current limit function can be disabled by connecting the ADJ pin to ground and ISENSE to VIN.

CATCH DIODE SELECTION (D1)

The important parameters for the catch diode are the peak current, the peak reverse voltage, and the average

power dissipation. The average current through the diode can be calculated as following.

ID_AVE = IOUT

* (1 − D)

(14)

The off state voltage across the catch diode is approximately equal to the input voltage. The peak reverse

voltage rating must be greater than input voltage. In nearly all cases a Schottky diode is recommended. In low

output voltage applications a low forward voltage provides improved efficiency. For high temperature

applications, diode leakage current may become significant and require a higher reverse voltage rating to

achieve acceptable performance.

P-CHANNEL MOSFET SELECTION (Q1)

The important parameters for the PFET are the maximum Drain-Source voltage (VDS), the on resistance (RDSON),

Current rating, and the input capacitance.

The voltage across the PFET when it is turned off is equal to the sum of the input voltage and the diode forward

voltage. The VDS must be selected to provide some margin beyond the input voltage.

PFET drain current, Id, must be rated higher than the peak inductor current, IIND-PEAK.

Depending on operating conditions, the PGATE voltage may fall as low as VIN - 8.3V. Therefore, a PFET must

be selected with a VGS greater than the maximum PGATE swing voltage.

As input voltage desreases below 9V, PGATE swing voltage may also decrease. At 5.0V input the PGATE will

swing from VIN to VIN - 4.6V. To ensure that the PFET turns on quickly and completely, a low threshold PFET

should be used when the input voltage is less than 7V.

However, PFET switching losses will increase as the VGS threshold decreases. Therefore, whenever possible, a

high threshold PFET should be selected. Total power loss in the FET can be approximated using the following

equation:

PDswitch = RDSON*IOUT

2*D + F*I

OUT*VIN*(ton + toff)/2

(15)

where:

ton = FET turn on time

toff = FET turn off time

A value of 10ns to 20ns is typical for ton and toff.

A PFET should be selected with a turn on rise time of less than 100ns. Slower rise times will degrade efficiency,

can cause false current limiting, and in extreme cases may cause abnormal spiking at the PGATE pin.

The RDSON is used in determining the current limit resistor value, RADJ. Note that the RDSON has a positive

temperature coefficient. At 100°C, the RDSON may be as much as 150% higher than the 25°C value. This

increase in RDSON must be considered it when determining RADJ in wide temperature range applications. If the

current limit is set based upon 25°C ratings, then false current limiting can occur at high temperature.

Keeping the gate capacitance below 2000pF is recommended to keep switching losses and transition times low.

This will also help keep the PFET drive current low, which will improve efficiency and lower the power dissipation

within the controller.

As gate capacitance increases, operating frequency should be reduced and as gate capacitance decreases

operating frequency can be increased.

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