5

AT25DF011

DS-25DF011–032A–4/2014

4.

Memory Array

To provide the greatest flexibility, the memory array of the AT25DF011 can be erased in three levels of granularity

including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing

both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the

breakdown of each erase level.

Figure 4-1.

Memory Architecture Diagram

5.

Device Operation

The AT25DF011 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI

Master. The SPI Master communicates with the AT25DF011 via the SPI bus which is comprised of four signal lines: Chip

Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).

The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the

SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25DF011

supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the

polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any

data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge

of SCK.

32KB

4KB

1-256 Byte

Block Erase

Block Erase

Page Program

(52h Command)

(20h Command)

(02h Command)

4KB

01FFFFh – 01F000h

256 Bytes

01FFFFh – 01FF00h

4KB

01EFFFh – 01E000h

256 Bytes

01FEFFh – 01FE00h

4KB

01DFFFh – 01D000h

256 Bytes

01FDFFh – 01FD00h

4KB

01CFFFh – 01C000h

256 Bytes

01FCFFh – 01FC00h

4KB

01BFFFh – 01B000h

256 Bytes

01FBFFh – 01FB00h

4KB

01AFFFh – 01A000h

256 Bytes

01FAFFh – 01FA00h

4KB

019FFFh – 019000h

256 Bytes

01F9FFh – 01F900h

4KB

018FFFh – 018000h

256 Bytes

01F8FFh – 01F800h

4KB

017FFFh – 017000h

256 Bytes

01F7FFh – 01F700h

4KB

016FFFh – 016000h

256 Bytes

01F6FFh – 01F600h

4KB

015FFFh – 015000h

256 Bytes

01F5FFh – 01F500h

4KB

014FFFh – 014000h

256 Bytes

01F4FFh – 01F400h

4KB

013FFFh – 013000h

256 Bytes

01F3FFh – 01F300h

4KB

012FFFh – 012000h

256 Bytes

01F2FFh – 01F200h

4KB

011FFFh – 011000h

256 Bytes

01F1FFh – 01F100h

4KB

010FFFh – 010000h

4KB

00FFFFh – 00F000h

4KB

00EFFFh – 00E000h

256 Bytes

000EFFh – 000E00h

4KB

00DFFFh – 00D000h

256 Bytes

000DFFh – 000D00h

4KB

00CFFFh – 00C000h

256 Bytes

000CFFh – 000C00h

4KB

00BFFFh – 00B000h

256 Bytes

000BFFh – 000B00h

4KB

00AFFFh – 00A000h

256 Bytes

000AFFh – 000A00h

4KB

009FFFh – 009000h

256 Bytes

0009FFh – 000900h

4KB

008FFFh – 008000h

256 Bytes

0008FFh – 000800h

4KB

4KB

4KB

4KB

004FFFh – 004000h

256 Bytes

0004FFh – 000400h

4KB

003FFFh – 003000h

256 Bytes

0003FFh – 000300h

4KB

002FFFh – 002000h

256 Bytes

0002FFh – 000200h

4KB

001FFFh – 001000h

256 Bytes

0001FFh – 000100h

4KB

000FFFh – 000000h

256 Bytes

0000FFh – 000000h

Block Erase Detail

Page Program Detail

Page Address

Block Address

32KB

32KB

Range

Range

32KB

32KB

007FFFh – 007000h

256 Bytes

0007FFh – 000700h

006FFFh – 006000h

256 Bytes

0006FFh – 000600h

005FFFh – 005000h

256 Bytes

0005FFh – 000500h